Issued Patents All Time
Showing 25 most recent of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423058 | Systolic array with input reduction to multiple reduced inputs | Paul Gilbert Meyer, Ron Diamant, Joshua W. Bowman, Nishith Desai, Thomas Elmer | 2025-09-23 |
| 12333274 | Data-type-aware clock-gating | Joshua W. Bowman, Sundeep Amirineni, Nishith Desai, Ron Diamant | 2025-06-17 |
| 12210940 | On-circuit activity monitoring for modifying integrated circuit processing | Ron Diamant | 2025-01-28 |
| 12197308 | On-circuit utilization monitoring for a systolic array | Ron Diamant | 2025-01-14 |
| 12182064 | Multiple accumulate busses in a systolic array | Sundeep Amirineni, Thomas Elmer | 2024-12-31 |
| 12137049 | Extending virtual routing and forwarding | Bijendra Singh, Kari Ann OBrien, Kiran Kalkunte Seshadri | 2024-11-05 |
| 12132028 | Semiconductor package with capacitance die | Bassam Abdel-Dayem | 2024-10-29 |
| 12067492 | Processing for multiple input data sets in a multi-layer neural network | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2024-08-20 |
| 12008466 | Processor with control flow | Randy Renfu Huang, Ron Diamant | 2024-06-11 |
| 11907144 | Early semaphore update | Raymond Scott Whiteside | 2024-02-20 |
| 11900024 | Simulating network packets in a packet processing pipeline | — | 2024-02-13 |
| 11899551 | On-chip software-based activity monitor to configure throttling at a hardware-based activity monitor | — | 2024-02-13 |
| 11880682 | Systolic array with efficient input reduction and extended array performance | Paul Gilbert Meyer, Ron Diamant, Joshua W. Bowman, Nishith Desai, Thomas Elmer | 2024-01-23 |
| 11848849 | Testing computer networks in real time | — | 2023-12-19 |
| 11816446 | Systolic array component combining multiple integer and floating-point data types | Thomas Elmer | 2023-11-14 |
| 11797853 | Processing for multiple input data sets | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2023-10-24 |
| 11762803 | Multiple accumulate busses in a systolic array | Sundeep Amirineni, Thomas Elmer | 2023-09-19 |
| 11729300 | Generating programmatically defined fields of metadata for network packets | Timothy David Gasser, Robert Michael Johnson, Mark Bradley Davis, Vithal Dattatraya Shirodkar | 2023-08-15 |
| 11546336 | Independently configurable access device stages for processing interconnect access requests | Mark Anthony Banse | 2023-01-03 |
| 11528187 | Dynamically configurable networking device interfaces for directional capacity modifications | Kiran Kalkunte Seshadri, Jamie Plenderleith, Alan M. Judge, Gianluca Grilli, Alaa Adel Mahdi Hayder | 2022-12-13 |
| 11520731 | Arbitrating throttling recommendations for a systolic array | Ron Diamant | 2022-12-06 |
| 11487675 | Collecting statistics for persistent memory | — | 2022-11-01 |
| 11475306 | Processing for multiple input data sets | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2022-10-18 |
| 11467983 | Independently configurable interleaving for interconnect access requests | Mark Anthony Banse | 2022-10-11 |
| 11461631 | Scheduling neural network computations based on memory capacity | Dana Michelle Vantrease, Ron Diamant, Randy Renfu Huang | 2022-10-04 |