Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12265492 | Circular buffer for input and output of tensor computations | Harshit Khaitan, Yu-Hsin Chen, Kyong Ho Lee, Xu Chen | 2025-04-01 |
| 12197362 | Batch matrix multiplication operations in a machine learning accelerator | Yu-Hsin Chen, Kyong Ho Lee, Harshit Khaitan | 2025-01-14 |
| 12001893 | Distributed synchronization scheme | Harshit Khaitan, Xu Chen, Miguel Guerrero, Simon James Hollis | 2024-06-04 |
| 11972349 | Flexible compute array utilization in a tensor processor | Yu-Hsin Chen, Vikas Chandra | 2024-04-30 |
| 11954025 | Systems and methods for reading and writing sparse data in a neural network accelerator | Ganesh Venkatesh, Pierce I-Jen Chuang, Meng Li | 2024-04-09 |
| 11709783 | Tensor data distribution using grid direct-memory access (DMA) controller | Xu Chen, Harshit Khaitan, Yu-Hsin Chen | 2023-07-25 |
| 11704562 | Architecture for virtual instructions | Harshit Khaitan, Miguel Guerrero, Simon James Hollis | 2023-07-18 |
| 11698529 | Systems and methods for distributing a neural network across multiple computing devices | Pierce I-Jen Chuang, Vikas Chandra, Ganesh Venkatesh | 2023-07-11 |
| 11675998 | System and method for performing small channel count convolutions in energy-efficient input operand stationary accelerator | Ganesh Venkatesh, Pierce I-Jen Chuang, Meng Li | 2023-06-13 |
| 11630770 | Systems and methods for reading and writing sparse data in a neural network accelerator | Ganesh Venkatesh, Pierce I-Jen Chuang, Meng Li | 2023-04-18 |
| 11385864 | Counter based multiply-and-accumulate circuit for neural network | Pierce I-Jen Chuang | 2022-07-12 |
| 11301545 | Power efficient multiply-accumulate circuitry | — | 2022-04-12 |
| 10977002 | System and method for supporting alternate number format for efficient multiplication | Ganesh Venkatesh, Pierce I-Jen Chuang, Meng Li, Vikas Chandra | 2021-04-13 |
| 10122384 | Logical interleaver | Vikas Chandra, Gary Dale Carpenter | 2018-11-06 |
| 9922152 | Computer implemented system and method for reducing failure in time soft errors of a circuit design | Vikas Chandra | 2018-03-20 |