Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Anton J. deVilliers

TLTokyo Electron Limited: 148 patents #2 of 5,567Top 1%
Micron: 48 patents #378 of 6,345Top 6%
NTNanya Technology: 3 patents #232 of 775Top 30%
Clifton Park, NY: #4 of 1,126 inventorsTop 1%
New York: #148 of 115,490 inventorsTop 1%
Overall (All Time): #3,395 of 4,157,543Top 1%
199 Patents All Time

Issued Patents All Time

Showing 51–75 of 199 patents

Patent #TitleCo-InventorsDate
11417526 Multiple patterning processes David L. O'Meara, Eric Chih-Fang Liu, Jodi Grzeskowiak, Akiteru Ko, Anthony Dip 2022-08-16
11393694 Method for planarization of organic films Robert Brandt, Jeffrey Smith, Jodi Grzeskowiak, Daniel Fulford 2022-07-19
11383211 Point-of-use dynamic concentration delivery system with high flow and high uniformity Ronald Nasman, Lior Huli, Rodney L. Robison, Norman A. Jacobson, Jr., James Grootegoed 2022-07-12
11360388 Critical dimension correction via calibrated trim dosing Ronald Nasman, Jeffrey Smith 2022-06-14
11342427 3D directed self-assembly for nanostructures Jodi Grzeskowiak, Lars Liebmann, Daniel Chanemougame 2022-05-24
11335599 Self-aligned contacts for 3D logic and memory Lars Liebmann, Jeffrey Smith, Kandabara Tapily 2022-05-17
11335566 Method for planarization of spin-on and CVD-deposited organic films Daniel Fulford, Jodi Grzeskowiak 2022-05-17
11322401 Reverse contact and silicide process for three-dimensional semiconductor devices Jeffrey Smith, Lars Liebmann, Daniel Chanemougame, Hiroki Niimi, Kandabara Tapily +2 more 2022-05-03
11264289 Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner +1 more 2022-03-01
11264274 Reverse contact and silicide process for three-dimensional logic devices Jeffrey Smith, Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Lars Liebmann +2 more 2022-03-01
11251200 Coaxial contacts for 3D logic and memory Lars Liebmann, Jeffrey Smith, Kandabara Tapily 2022-02-15
11251080 Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits Mark I. Gardner, H. Jim Fulford 2022-02-15
11247309 Substrate holding apparatus and method for shape metrology Hoyoung Kang 2022-02-15
11217583 Architecture design of monolithically integrated 3D CMOS logic and memory Lars Liebmann, Jeffrey Smith, Kandabara Tapily 2022-01-04
11201148 Architecture for monolithic 3D integration of semiconductor devices Lars Liebmann, Jeffrey Smith 2021-12-14
11201051 Method for layer by layer growth of conformal films Jodi Grzeskowiak, Daniel Fulford 2021-12-14
11171208 High performance circuit applications using stacked 3D metal lines H. Jim Fulford, Mark I. Gardner 2021-11-09
11133206 Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking H. Jim Fulford, Anthony R. Schepis 2021-09-28
11114381 Power distribution network for 3D logic and memory Lars Liebmann, Jeffrey Smith, Kandabara Tapily 2021-09-07
11107682 Method for patterning a substrate using a layer with multiple materials 2021-08-31
11101152 Phase mixture temperature controlled hot plate 2021-08-24
11069616 Horizontal programmable conducting bridges between conductive lines H. Jim Fulford, Mark I. Gardner 2021-07-20
11049721 Method and process for forming memory hole patterns Toshiharu Wada, Akiteru Ko 2021-06-29
11049700 Atmospheric plasma processing systems and methods for manufacture of microelectronic workpieces Mirko Vukovic, Brandon Byrns 2021-06-29
10998244 System and method for temperature control in plasma processing system 2021-05-04