Issued Patents All Time
Showing 51–75 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11769831 | High performance floating body VFET with dielectric core | Mark I. Gardner | 2023-09-26 |
| 11764200 | High density architecture design for 3D logic and 3D memory circuits | Mark I. Gardner | 2023-09-19 |
| 11756836 | 3D device layout and method using advanced 3D isolation | Mark I. Gardner, Partha Mukhopadhyay | 2023-09-12 |
| 11721592 | Method of making vertical semiconductor nanosheets with diffusion breaks | Mark I. Gardner | 2023-08-08 |
| 11721582 | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits | Mark I. Gardner, Anton J. deVilliers | 2023-08-08 |
| 11721551 | Localized stress regions for three-dimension chiplet formation | Anton J. deVilliers, Daniel Fulford, Anthony R. Schepis, Mark I. Gardner | 2023-08-08 |
| 11695058 | Method of expanding 3D device architectural designs for enhanced performance | Mark I. Gardner | 2023-07-04 |
| 11694957 | Programmable connection segment and method of forming the same | Mark I. Gardner, Anton J. deVilliers | 2023-07-04 |
| 11688642 | Localized stress regions for three-dimension chiplet formation | Anton J. deVilliers, Daniel Fulford, Anthony R. Schepis, Mark I. Gardner | 2023-06-27 |
| 11652139 | Three-dimensional universal CMOS device | Mark I. Gardner | 2023-05-16 |
| 11640937 | Horizontal programmable conducting bridges between conductive lines | Mark I. Gardner, Anton J. deVilliers | 2023-05-02 |
| 11631671 | 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same | Anton J. deVilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann +1 more | 2023-04-18 |
| 11626329 | Metal connections and routing for advanced 3D layout designs | Mark I. Gardner | 2023-04-11 |
| 11610993 | 3D semiconductor apparatus manufactured with a plurality of substrates and method of manufacture thereof | Mark I. Gardner | 2023-03-21 |
| 11594535 | High performance nanosheet fabrication method with enhanced high mobility channel elements | Mark I. Gardner | 2023-02-28 |
| 11557657 | High density 3D layout enhancement of multiple CMOS devices | Mark I. Gardner | 2023-01-17 |
| 11557655 | Device and method of forming with three-dimensional memory and three-dimensional logic | Mark I. Gardner | 2023-01-17 |
| 11557519 | Optimum high density 3D device layout and method of fabrication | Mark I. Gardner | 2023-01-17 |
| 11552080 | Method of making multiple nano layer transistors to enhance a multiple stack CFET performance | Mark I. Gardner | 2023-01-10 |
| 11527545 | Architecture design and process for 3D logic and 3D memory | Mark I. Gardner | 2022-12-13 |
| 11521972 | High performance multi-dimensional device and logic integration | Mark I. Gardner | 2022-12-06 |
| 11515306 | Unified architectural design for enhanced 3D circuit options | Mark I. Gardner | 2022-11-29 |
| 11508625 | Method of making a continuous channel between 3D CMOS | Mark I. Gardner | 2022-11-22 |
| 11488902 | Split substrate interposer | Arya Bhattacherjee | 2022-11-01 |
| 11410992 | 3D semiconductor apparatus manufactured with a cantilever structure and method of manufacture thereof | Mark I. Gardner | 2022-08-09 |