Issued Patents All Time
Showing 26–50 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148687 | Split substrate interposer with integrated passive device | Arya Bhattacherjee | 2024-11-19 |
| 12148668 | Stackable semiconductor device with 2D material layer and methods of manufacturing thereof | Mark I. Gardner | 2024-11-19 |
| 12133387 | 3D memory with conductive dielectric channel integrated with logic access transistors | Mark I. Gardner, Partha Mukhopadhyay | 2024-10-29 |
| 12131956 | Ultra dense 3D routing for compact 3D designs | Mark I. Gardner, Partha Mukhopadhyay | 2024-10-29 |
| 12114480 | Method of making of plurality of 3D vertical logic elements integrated with 3D memory | Mark I. Gardner, Partha Mukhopadhyay | 2024-10-08 |
| 12087817 | High performance 3D vertical transistor device enhancement design | Mark I. Gardner | 2024-09-10 |
| 12087640 | High density logic formation using multi-dimensional laser annealing | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2024-09-10 |
| 12068205 | 3D high density compact metal first approach for hybrid transistor designs without using epitaxial growth | Mark I. Gardner, Partha Mukhopadhyay | 2024-08-20 |
| 12040236 | 3D devices with 3D diffusion breaks and method of forming the same | Mark I. Gardner | 2024-07-16 |
| 12020990 | Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks | Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner +1 more | 2024-06-25 |
| 12009355 | 3D stacked DRAM with 3D vertical circuit design | Mark I. Gardner, Partha Mukhopadhyay | 2024-06-11 |
| 12002809 | Method to enhance 3D horizontal nanosheets device performance | Mark I. Gardner | 2024-06-04 |
| 12001147 | Precision multi-axis photolithography alignment correction using stressor film | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, Anton J. deVilliers | 2024-06-04 |
| 11978735 | Transistor stack of vertical channel ferroelectric FETs and methods of forming the transistor stack | Mark I. Gardner, Robert D. Clark | 2024-05-07 |
| 11942536 | Semiconductor device having channel structure with 2D material | Robert D. Clark, Mark I. Gardner | 2024-03-26 |
| 11908747 | Method for designing three dimensional metal lines for enhanced device performance | Mark I. Gardner | 2024-02-20 |
| 11894378 | Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance | Mark I. Gardner | 2024-02-06 |
| 11887897 | High precision 3D metal stacking for a plurality of 3D devices | Mark I. Gardner | 2024-01-30 |
| 11876125 | Method of making a plurality of high density logic elements with advanced CMOS device layout | Mark I. Gardner | 2024-01-16 |
| 11862497 | Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking | Anthony R. Schepis, Anton J. deVilliers | 2024-01-02 |
| 11842919 | Method of making 3D isolation | Mark I. Gardner | 2023-12-12 |
| 11830876 | Three-dimensional device with self-aligned vertical interconnection | Mark I. Gardner, Partha Mukhopadhyay | 2023-11-28 |
| 11810854 | Multi-dimensional vertical switching connections for connecting circuit elements | Mark I. Gardner, Anton J. deVilliers | 2023-11-07 |
| 11777015 | Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits | Mark I. Gardner | 2023-10-03 |
| 11776954 | Semiconductor apparatus having a silicide between two devices | Mark I. Gardner | 2023-10-03 |