Issued Patents All Time
Showing 76–100 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11410888 | Method of making 3D CMOS with integrated channel and S/D regions | Mark I. Gardner | 2022-08-09 |
| 11393813 | Method of architecture design for enhanced 3D device performance | Mark I. Gardner | 2022-07-19 |
| 11362091 | Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance | Mark I. Gardner | 2022-06-14 |
| 11342339 | Method of making six transistor SRAM cell using connections between 3D transistor stacks | Mark I. Gardner | 2022-05-24 |
| 11302587 | Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices | Mark I. Gardner | 2022-04-12 |
| 11282828 | High density architecture design for 3D logic and 3D memory circuits | Mark I. Gardner | 2022-03-22 |
| 11276704 | Device and method of forming with three-dimensional memory and three-dimensional logic | Mark I. Gardner | 2022-03-15 |
| 11264289 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner +1 more | 2022-03-01 |
| 11251159 | High performance CMOS using 3D device layout | Mark I. Gardner | 2022-02-15 |
| 11251080 | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits | Mark I. Gardner, Anton J. deVilliers | 2022-02-15 |
| 11222964 | Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits | Mark I. Gardner | 2022-01-11 |
| 11195832 | High performance nanosheet fabrication method with enhanced high mobility channel elements | Mark I. Gardner | 2021-12-07 |
| 11177250 | Method for fabrication of high density logic and memory for advanced circuit architecture | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-11-16 |
| 11171208 | High performance circuit applications using stacked 3D metal lines | Mark I. Gardner, Anton J. deVilliers | 2021-11-09 |
| 11139213 | Method of making 3D source drains with hybrid stacking for optimum 3D logic layout | Mark I. Gardner | 2021-10-05 |
| 11133310 | Method of making multiple nano layer transistors to enhance a multiple stack CFET performance | Mark I. Gardner | 2021-09-28 |
| 11133206 | Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking | Anthony R. Schepis, Anton J. deVilliers | 2021-09-28 |
| 11114346 | High density logic formation using multi-dimensional laser annealing | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-09-07 |
| 11107733 | Multi-dimensional planes of logic and memory formation using single crystal silicon orientations | Mark I. Gardner, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-08-31 |
| 11069616 | Horizontal programmable conducting bridges between conductive lines | Mark I. Gardner, Anton J. deVilliers | 2021-07-20 |
| 8575716 | Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation | James Mathew, Brett D. Lowe, Yunjun Ho, Jie Sun, Zhaoli Sun | 2013-11-05 |
| 8461016 | Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation | James Mathew, Brett D. Lowe, Yunjun Ho, Jie Sun, Zhaoli Sun | 2013-06-11 |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites | Mark I. Gardner, Derick J. Wristers | 2005-12-27 |
| 6911707 | Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance | Mark I. Gardner, Dim-Lee Kwong | 2005-06-28 |
| 6746616 | Method and apparatus for providing etch uniformity using zoned temperature control | Jeremy Lansford | 2004-06-08 |