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Home › Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

US Patent 6146978 · Granted Nov 14, 2000

Estimated economic value: $4,365,000 ⓘ

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