Issued Patents All Time
Showing 26–50 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6376330 | Dielectric having an air gap formed between closely spaced interconnect lines | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 2002-04-23 |
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2002-04-16 |
| 6358803 | Method of fabricating a deep source/drain | Jon D. Cheek | 2002-03-19 |
| 6353253 | Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, William S. Brennan | 2002-03-05 |
| 6326298 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 2001-12-04 |
| 6323095 | Method for reducing junction capacitance using a halo implant photomask | Jon D. Cheek, Robert Dawson | 2001-11-27 |
| 6274415 | Self-aligned Vt implant | Jon D. Cheek, Derick J. Wristers, James F. Buller | 2001-08-14 |
| 6261885 | Method for forming integrated circuit gate conductors from dual layers of polysilicon | Jon D. Cheek, Daniel Kadosh | 2001-07-17 |
| 6259142 | Multiple split gate semiconductor device and fabrication method | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Bradley T. Moore +1 more | 2001-07-10 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh +2 more | 2001-05-01 |
| 6208015 | Interlevel dielectric with air gaps to lessen capacitive coupling | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan | 2001-03-27 |
| 6201278 | Trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2001-03-13 |
| 6197645 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2001-03-06 |
| 6188233 | Method for determining proximity effects on electrical characteristics of semiconductor devices | John L. Nistler | 2001-02-13 |
| 6188114 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2001-02-13 |
| 6166354 | System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more | 2000-12-26 |
| 6153833 | Integrated circuit having interconnect lines separated by a dielectric having a capping layer | Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 2000-11-28 |
| 6150721 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan | 2000-11-21 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-11-14 |
| 6137145 | Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon | Jon D. Cheek, Daniel Kadosh | 2000-10-24 |
| 6127264 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan | 2000-10-03 |
| 6127719 | Subfield conductive layer and method of manufacture | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 2000-10-03 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-08-29 |
| 6100146 | Method of forming trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2000-08-08 |
| 6096639 | Method of forming a local interconnect by conductive layer patterning | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Bradley T. Moore +1 more | 2000-08-01 |