Issued Patents All Time
Showing 51–75 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6096616 | Fabrication of a non-ldd graded p-channel mosfet | John L. Nistler | 2000-08-01 |
| 6091149 | Dissolvable dielectric method and structure | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, William S. Brennan | 2000-07-18 |
| 6090703 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Fred N. Hause, Robert Dawson | 2000-07-18 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Bradley T. Moore +1 more | 2000-07-11 |
| 6080629 | Ion implantation into a gate electrode layer using an implant profile displacement layer | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2000-06-27 |
| 6074904 | Method and structure for isolating semiconductor devices after transistor formation | Thomas E. Spikes, Jr., Mark I. Gardner, Robert Dawson | 2000-06-13 |
| 6060345 | Method of making NMOS and PMOS devices with reduced masking steps | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more | 2000-05-09 |
| 6054356 | Transistor and process of making a transistor having an improved LDD masking material | Robert Dawson, Fred N. Hause | 2000-04-25 |
| 6048785 | Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching | H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-04-11 |
| 6049134 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 2000-04-11 |
| 6043544 | Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric | Robert Dawson | 2000-03-28 |
| 6031289 | Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, William S. Brennan | 2000-02-29 |
| 6030752 | Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device | H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 2000-02-29 |
| 6027859 | Semiconductor substrate having extended scribe line test structure and method of fabrication thereof | Robert Dawson, Fred N. Hause | 2000-02-22 |
| 5998293 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1999-12-07 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device | Mark I. Gardner, Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause +1 more | 1999-11-02 |
| 5968843 | Method of planarizing a semiconductor topography using multiple polish pads | Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1999-10-19 |
| 5963803 | Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths | Robert Dawson, Charles E. May | 1999-10-05 |
| 5962894 | Trench transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 1999-10-05 |
| 5953626 | Dissolvable dielectric method | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, William S. Brennan | 1999-09-14 |
| 5937299 | Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more | 1999-08-10 |
| 5930642 | Transistor with buried insulative layer beneath the channel region | Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 1999-07-27 |
| 5930634 | Method of making an IGFET with a multilevel gate | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Bradley T. Moore +1 more | 1999-07-27 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner | Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1999-07-20 |
| 5926713 | Method for achieving global planarization by forming minimum mesas in large field areas | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, William S. Brennan | 1999-07-20 |