MM

Mark W. Michael

AM AMD: 106 patents #25 of 9,279Top 1%
Globalfoundries: 6 patents #578 of 4,424Top 15%
Harris: 2 patents #731 of 2,288Top 35%
📍 Palm Bay, FL: #2 of 673 inventorsTop 1%
🗺 Florida: #111 of 67,251 inventorsTop 1%
Overall (All Time): #10,937 of 4,157,543Top 1%
115
Patents All Time

Issued Patents All Time

Showing 76–100 of 115 patents

Patent #TitleCo-InventorsDate
5924008 Integrated circuit having local interconnect for reducing signal cross coupled noise Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan 1999-07-13
5918129 Method of channel doping using diffusion from implanted polysilicon H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 1999-06-29
5918126 Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 1999-06-29
5899732 Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device Mark I. Gardner, Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause +1 more 1999-05-04
5899727 Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, William S. Brennan 1999-05-04
5894168 Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan 1999-04-13
5888675 Reticle that compensates for radiation-induced lens error in a photolithographic system Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more 1999-03-30
5885887 Method of making an igfet with selectively doped multilevel polysilicon gate Frederick N. Hause, Robert Dawson, H. Jim Fulford Jr., Mark I. Gardner, Bradley T. Moore +1 more 1999-03-23
5885877 Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh +2 more 1999-03-23
5877058 Method of forming an insulated-gate field-effect transistor with metal spacers Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more 1999-03-02
5869378 Method of reducing overlap between gate electrode and LDD region — 1999-02-09
5854515 Integrated circuit having conductors of enhanced cross-sectional area Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan 1998-12-29
5854131 Integrated circuit having horizontally and vertically offset interconnect lines Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford Jr., Fred N. Hause, William S. Brennan 1998-12-29
5851913 Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process William S. Brennan, Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay 1998-12-22
5851891 IGFET method of forming with silicide contact on ultra-thin gate Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 1998-12-22
5851889 Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric Robert Dawson 1998-12-22
5850105 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan 1998-12-15
5847462 Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan, Fred N. Hause, Robert Dawson 1998-12-08
5846876 Integrated circuit which uses a damascene process for producing staggered interconnect lines Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan 1998-12-08
5840451 Individually controllable radiation sources for providing an image pattern in a photolithographic system Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more 1998-11-24
5837557 Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 1998-11-17
5830773 Method for forming semiconductor field region dielectrics having globally planarized upper surfaces William S. Brennan, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford 1998-11-03
5827776 Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan 1998-10-27
5827761 Method of making NMOS and devices with sequentially formed gates having different gate lengths H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Bradley T. Moore +1 more 1998-10-27
5814555 Interlevel dielectric with air gaps to lessen capacitive coupling Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, William S. Brennan 1998-09-29