Issued Patents All Time
Showing 101–115 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5801075 | Method of forming trench transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 1998-09-01 |
| 5792706 | Interlevel dielectric with air gaps to reduce permitivity | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-08-11 |
| 5783864 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, William S. Brennan, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1998-07-21 |
| 5783481 | Semiconductor interlevel dielectric having a polymide for producing air gaps | William S. Brennan, Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay | 1998-07-21 |
| 5767000 | Method of manufacturing subfield conductive layer | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1998-06-16 |
| 5767012 | Method of forming a recessed interconnect structure | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, William S. Brennan | 1998-06-16 |
| 5766803 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-06-16 |
| 5759913 | Method of formation of an air gap within a semiconductor dielectric by solvent desorption | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, William S. Brennan | 1998-06-02 |
| 5733798 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, William S. Brennan | 1998-03-31 |
| 5723238 | Inspection of lens error associated with lens heating in a photolithographic system | Bradley T. Moore, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 1998-03-03 |
| 5717242 | Integrated circuit having local interconnect for reduing signal cross coupled noise | Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, William S. Brennan | 1998-02-10 |
| 5710054 | Method of forming a shallow junction by diffusion from a silicon-based spacer | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 1998-01-20 |
| 5679605 | Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process | William S. Brennan, Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay | 1997-10-21 |
| 4701780 | Integrated verticle NPN and vertical oxide fuse programmable memory cell | Kevin T. Hankins, Jay D. Moser, Sr., Brian K. Rosier | 1987-10-20 |
| 4635345 | Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell | Kevin T. Hankins, Brian K. Rosier | 1987-01-13 |