Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627138 | Apparatus and associated methods for capacitors with improved density and matching | Shuxian Chen, Yan Cui, Jeffrey T. Watt | 2017-04-18 |
| 9496268 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2016-11-15 |
| 9455338 | Methods for fabricating PNP bipolar junction transistors | Yanzhong Xu | 2016-09-27 |
| 9196749 | Programmable device with a metal oxide semiconductor field effect transistor | Charu Sardana, Qi Xiang, Bradley Jensen | 2015-11-24 |
| 9190332 | Method of fabricating integrated circuit transistors with multipart gate conductors | Jun Liu, Qi Xiang, Jeffrey Tung | 2015-11-17 |
| 9165640 | Method of using a PMOS pass gate | Jun Liu, Irfan Rahim, Qi Xiang | 2015-10-20 |
| 8933751 | High resolution capacitor | Wilson Wong, Weiqi Ding, Shuxian Chen, Simardeep Maangat | 2015-01-13 |
| 8921170 | Integrated circuits with asymmetric pass transistors | Jun Liu, Mark T. Chan, Irfan Rahim | 2014-12-30 |
| 8878334 | Integrated circuit resistors with reduced parasitic capacitance | Peter Smeys | 2014-11-04 |
| 8804407 | PMOS pass gate | Jun Liu, Irfan Rahim, Qi Xiang | 2014-08-12 |
| 8750026 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2014-06-10 |
| 8735983 | Integrated circuit transistors with multipart gate conductors | Jun Liu, Qi Xiang, Jeffrey Tung | 2014-05-27 |
| 8530976 | Memory element transistors with reversed-workfunction gate conductors | Qi Xiang, Jun Liu | 2013-09-10 |
| 8482963 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2013-07-09 |
| 8467240 | Integrated circuits with nonvolatile memory elements | Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Liu | 2013-06-18 |
| 8264214 | Very low voltage reference circuit | Qi Xiang, Simardeep Maangat, Jun Liu | 2012-09-11 |
| 8242581 | Mixed-gate metal-oxide-semiconductor varactors | Wilson Wong, Jun Liu, Qi Xiang, Jeffrey Tung | 2012-08-14 |
| 8138791 | Stressed transistors with reduced leakage | Jun Liu, Jeffrey Tung, Qi Xiang | 2012-03-20 |
| 8138797 | Integrated circuits with asymmetric pass transistors | Jun Liu, Mark T. Chan, Irfan Rahim | 2012-03-20 |
| 8116130 | Integrated circuits with nonvolatile memory elements | Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Liu | 2012-02-14 |
| 8081502 | Memory elements with body bias control | Irfan Rahim, Jun Liu, Andy L. Lee, William Bradley Vest, Lu Zhou +3 more | 2011-12-20 |
| 7952423 | Process/design methodology to enable high performance logic and analog circuits using a single process | Qi Xiang, Jeffrey Tung, Weiqi Ding | 2011-05-31 |
| 7812408 | Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers | Peter J. McElheny | 2010-10-12 |