Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627658 | Battery and battery pack | Yoshio TAKENOUCHI, Kenichi Takahashi | 2017-04-18 |
| 5942784 | Semiconductor device | Takayuki Harima, Kenichi Nakamura | 1999-08-24 |
| 5635850 | Intelligent test line system | — | 1997-06-03 |
| 5227319 | Method of manufacturing a semiconductor device | Shioji Ariizumi, Fumio Horiguchi, Fujio Masuoka | 1993-07-13 |
| 5095463 | Semiconductor memory device | Haruki Toda | 1992-03-10 |
| 4992389 | Making a self aligned semiconductor device | Shioji Ariizumi, Fumio Horiguchi, Fujio Masuoka | 1991-02-12 |
| 4881113 | Semiconductor integrated circuits with a protection device | Masaki Momodomi, Takaki Kumanomido | 1989-11-14 |
| 4800530 | Semiconductor memory system with dynamic random access memory cells | Yasuo Itoh, Fumio Horiguchi, Shigeyoshi Watanabe, Kazunori Ohuchi | 1989-01-24 |
| 4798794 | Method for manufacturing dynamic memory cell | Fujio Masuoka | 1989-01-17 |
| 4799193 | Semiconductor memory devices | Fumio Horiguchi, Yasuo Itoh, Masaki Momodomi | 1989-01-17 |
| 4763178 | Semiconductor memory device | Koji Sakui | 1988-08-09 |
| 4748596 | Semiconductor memory device with sense amplifiers | Yasuo Itoh | 1988-05-31 |
| 4725985 | Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device | Fujio Masuoka | 1988-02-16 |
| 4706249 | Semiconductor memory device having error detection/correction function | Kaoru Nakagawa, Kenji Natori, Fujio Masuoka | 1987-11-10 |
| 4688064 | Dynamic memory cell and method for manufacturing the same | Fujio Masuoka | 1987-08-18 |
| 4644184 | Memory clock pulse generating circuit with reduced peak current requirements | Naokazu Miyawaki | 1987-02-17 |
| 4636981 | Semiconductor memory device having a voltage push-up circuit | — | 1987-01-13 |
| 4630088 | MOS dynamic ram | Masaki Momodomi | 1986-12-16 |
| 4611237 | Semiconductor integrated circuit device | Kazunori Ohuchi, Kenji Natori | 1986-09-09 |
| 4564854 | Combined MOS/memory transistor structure | — | 1986-01-14 |
| 4492973 | MOS Dynamic memory cells and method of fabricating the same | — | 1985-01-08 |
| 4490628 | MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances | — | 1984-12-25 |
| 4433911 | Method of evaluating measure precision of patterns and photomask therefor | Shizuo Sawada, Norio Endo | 1984-02-28 |