SW

Shigeyoshi Watanabe

KT Kabushiki Kaisha Toshiba: 29 patents #884 of 21,451Top 5%
TO Toshiba: 2 patents #606 of 2,688Top 25%
DE Denso: 1 patents #6,940 of 11,792Top 60%
Overall (All Time): #114,065 of 4,157,543Top 3%
32
Patents All Time

Issued Patents All Time

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDate
8204670 Cruise control system using instruction sent from switch — 2012-06-19
6295241 Dynamic random access memory device Tsuneaki Fuse, Koji Sakui, Masako Ohta, Yukihito Oowaki, Kenji Numata +1 more 2001-09-25
6292390 Semiconductor device Koji Sakui, Takehiro Hasegawa, Fujio Masuoka, Tsuneaki Fuse, Toshiki Seshita +3 more 2001-09-18
6232822 Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism Koji Sakui, Takehiro Hasegawa, Fujio Masuoka, Tsuneaki Fuse, Toshiki Seshita +3 more 2001-05-15
RE36993 Dynamic random access memory device with the combined open/folded bit-line pair arrangement Daisaburo Takashima 2000-12-19
5892724 NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines Takehiro Hasegawa, Yukihito Oowaki, Fujio Masuoka, Ryu Ogiwara, Shinichiro Shiratake 1999-04-06
5838038 Dynamic random access memory device with the combined open/folded bit-line pair arrangement Daisaburo Takashima, Tohru Ozaki, Takeshi Hamamoto, Yukihito Oowaki 1998-11-17
5732010 Dynamic random access memory device with the combined open/folded bit-line pair arrangement Daisaburo Takashima 1998-03-24
5717625 Semiconductor memory device Takehiro Hasegawa, Yukihito Oowaki, Ken Maeda, Mitsuo Saito, Masako Yoshida +2 more 1998-02-10
5625602 NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines Takehiro Hasegawa, Yukihito Oowaki, Fujio Masuoka, Ryu Ogiwara, Shinichiro Shiratake 1997-04-29
5555519 Dynamic random access memory device with the combined open/folded bit-line pair arrangement Daisaburo Takashima 1996-09-10
5508957 Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through Masaki Momodomi, Fujio Masuoka, Yasuo Itoh, Hiroshi Iwahashi, Yoshihisa Iwata +6 more 1996-04-16
5467303 Semiconductor memory device having register groups for writing and reading data Takehiro Hasegawa, Fujio Masuoka 1995-11-14
5416350 Semiconductor device with vertical transistors connected in series between bit lines — 1995-05-16
5397723 Process for forming arrayed field effect transistors highly integrated on substrate Riichiro Shirota, Masaki Momodomi, Ryozo Nakayama, Seiichi Aritome, Ryouhei Kirisawa +1 more 1995-03-14
5396450 Dynamic random access memory device with the combined open/folded bit-line pair arrangement Daisaburo Takashima 1995-03-07
5363325 Dynamic semiconductor memory device having high integration density Kazumasa Sunouchi, Tsuneaki Fuse, Akihiro Nitayama, Takehiro Hasegawa, Fumio Horiguchi +1 more 1994-11-08
5194762 MOS-type charging circuit Takahiko Hara, Syuso Fujii 1993-03-16
5088060 Electrically erasable programmable read-only memory with NAND memory cell structure Tetsuo Endoh, Riichiro Shirota, Masaki Momodomi, Tomoharu Tanaka, Fujio Masuoka 1992-02-11
5060194 Semiconductor memory device having a BICMOS memory cell Koji Sakui, Tsuneaki Fuse, Takehiro Hasegawa, Fujio Masuoka 1991-10-22
5038191 Semiconductor memory device Takehiro Hasegawa, Koji Sakui, Fujio Masuoka 1991-08-06
4996669 Electrically erasable programmable read-only memory with NAND memory cell structure Tetsuo Endoh, Riichiro Shirota, Masaki Momodomi, Tomoharu Tanaka, Fujio Masuoka 1991-02-26
4831433 Semiconductor device Mitsugi Oguara, Fumio Horiguchi 1989-05-16
4819207 High-speed refreshing rechnique for highly-integrated random-access memory Koji Sakui 1989-04-04
4811290 Semiconductor memory device — 1989-03-07