Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6104233 | Substrate structure of semi-conductor device | Mitsuru Shimizu, Kiyofumi Sakurai | 2000-08-15 |
| 5970006 | Semiconductor memory device having cell array divided into a plurality of cell blocks | Kenji Numata | 1999-10-19 |
| 5949109 | Semiconductor device having input protection circuit | Mitsuru Shimizu, Kenji Numata, Masaharu Wada | 1999-09-07 |
| RE36236 | Semiconductor memory device | Mitsuru Shimizu | 1999-06-29 |
| 5862090 | Semiconductor memory device having cell array divided into a plurality of cell blocks | Kenji Numata | 1999-01-19 |
| 5734619 | Semiconductor memory device having cell array divided into a plurality of cell blocks | Kenji Numata | 1998-03-31 |
| 5726475 | Semiconductor device having different impurity concentration wells | Shizuo Sawada, Masaki Ogihara | 1998-03-10 |
| 5594265 | Input protection circuit formed in a semiconductor substrate | Mitsuru Shimizu, Kenji Numata, Masaharu Wada | 1997-01-14 |
| 5420816 | Semiconductor memory apparatus with configured word lines to reduce noise | Masaki Ogihara | 1995-05-30 |
| 5374838 | Semiconductor device having different impurity concentration wells | Shizuo Sawada, Masaki Ogihara | 1994-12-20 |
| 5293055 | Semiconductor integrated circuit device | Takahiko Hara | 1994-03-08 |
| 5260226 | Semiconductor device having different impurity concentration wells | Shizuo Sawada, Masaki Ogihara | 1993-11-09 |
| 5238860 | Semiconductor device having different impurity concentration wells | Shizuo Sawada, Masaki Ogihara | 1993-08-24 |
| 5233558 | Semiconductor memory device capable of directly reading the potential of bit lines | Takeshi Nagai | 1993-08-03 |
| 5231607 | Semiconductor memory device | Munehiro Yoshida | 1993-07-27 |
| 5194762 | MOS-type charging circuit | Takahiko Hara, Shigeyoshi Watanabe | 1993-03-16 |
| 5150188 | Reference voltage generating circuit device | Takahiko Hara | 1992-09-22 |
| 5142492 | Semiconductor memory device | Mitsuru Shimizu | 1992-08-25 |
| 5119337 | Semiconductor memory device having burn-in test function | Mitsuru Shimizu, Shozo Saito | 1992-06-02 |
| 5079613 | Semiconductor device having different impurity concentration wells | Shizuo Sawada, Masaki Ogihara | 1992-01-07 |
| 5075752 | Bi-CMOS semiconductor device having memory cells formed in isolated wells | Takeo Maeda | 1991-12-24 |
| 5066997 | Semiconductor device | Kiyofumi Sakurai, Mitsuru Shimizu | 1991-11-19 |
| 5041893 | Semiconductor integrated circuit including an intrinsic MOS transistor for generating a reference voltage | Takeshi Nagai | 1991-08-20 |
| 5019729 | TTL to CMOS buffer circuit | Tohru Kimura, Takashi Ohsawa | 1991-05-28 |
| 5016071 | Dynamic memory device | Jumpei Kumagai | 1991-05-14 |