Issued Patents All Time
Showing 1–25 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8269346 | Semiconductor device and method of designing a wiring of a semiconductor device | Shoji Seta, Hideaki Ikuma | 2012-09-18 |
| 7487370 | Semiconductor device and system | Shinichiro Shiratake, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Masataka Matsui | 2009-02-03 |
| 7303965 | MIS transistor and method for producing same | Mizuki Ono, Mitsuhiro Noguchi, Daisaburo Takashima, Akira Nishiyama | 2007-12-04 |
| 7295456 | Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor | Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yoshiaki Takeuchi | 2007-11-13 |
| 7236035 | Semiconductor device adapted to minimize clock skew | Shinichiro Shiratake, Fumitoshi Hatori, Mototsugu Hamada, Hiroyuki Hara | 2007-06-26 |
| 7057917 | Ferroelectric memory with an intrinsic access transistor coupled to a capacitor | Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yoshiaki Takeuchi | 2006-06-06 |
| 6993691 | Series connected TC unit type ferroelectric RAM and test method thereof | Ryu Ogiwara, Daisaburo Takashima, Katsuhiko Hoya, Takeshi Watanabe | 2006-01-31 |
| 6906944 | Ferroelectric memory | Yoshiaki Takeuchi | 2005-06-14 |
| 6690047 | MIS transistor having a large driving current and method for producing the same | Mizuki Ono, Mitsuhiro Noguchi, Daisaburo Takashima, Akira Nishiyama | 2004-02-10 |
| 6671200 | Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit | Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yoshiaki Takeuchi | 2003-12-30 |
| 6643162 | Ferroelectric memory having a device responsive to current lowering | Yoshiaki Takeuchi | 2003-11-04 |
| 6611450 | Ferroelectric random access memory | Sumiko Doumae | 2003-08-26 |
| 6552922 | Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair | Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yoshiaki Takeuchi | 2003-04-22 |
| 6545323 | Semiconductor memory device including a pair of MOS transistors forming a detection circuit | Masako Yoshida, Makoto Yoshimi | 2003-04-08 |
| 6538952 | Random access memory with divided memory banks and data read/write architecture therefor | — | 2003-03-25 |
| 6522589 | Semiconductor apparatus and mode setting method for semiconductor apparatus | Tadashi Miyakawa, Daisaburo Takashima | 2003-02-18 |
| 6522569 | Semiconductor memory device | Tadashi Miyakawa | 2003-02-18 |
| 6510071 | Ferroelectric memory having memory cell array accessibility safeguards | — | 2003-01-21 |
| 6483737 | Ferroelectric memory device | Yoshiaki Takeuchi, Sumiko Doumae | 2002-11-19 |
| 6473330 | Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an equalization circuit | Ryu Ogiwara, Daisaburo Takashima, Sumio Tanaka, Yoshiaki Takeuchi | 2002-10-29 |
| 6473865 | Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal | Masahiro Kamoshida, Haruki Toda, Tsuneaki Fuse | 2002-10-29 |
| 6404696 | Random access memory with divided memory banks and data read/write architecture therefor | — | 2002-06-11 |
| 6392467 | Semiconductor integrated circuit | Tsuneaki Fuse | 2002-05-21 |
| 6393080 | Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal | Masahiro Kamoshida, Haruki Toda, Tsuneaki Fuse | 2002-05-21 |
| 6388484 | Clock control circuit | Masahiro Kamoshida, Haruki Toda, Tsuneaki Fuse | 2002-05-14 |