Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5978265 | Non-volatile semiconductor memory device with nand type memory cell arrays | Ryouhei Kirisawa, Riichiro Shirota, Seiichi Aritome, Masaki Momodomi, Yasuo Itoh +1 more | 1999-11-02 |
| 5824583 | Non-volatile semiconductor memory and method of manufacturing the same | Masamichi Asano, Hiroshi Iwahashi, Ryouhei Kirisawa, Satoshi Inoue, Riichiro Shirota +2 more | 1998-10-20 |
| 5597748 | Method of manufacturing NAND type EEPROM | Masamichi Asano, Hiroshi Iwahashi, Ryouhei Kirisawa, Satoshi Inoue, Riichiro Shirota +2 more | 1997-01-28 |
| 5508957 | Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through | Masaki Momodomi, Fujio Masuoka, Yasuo Itoh, Hiroshi Iwahashi, Yoshihisa Iwata +6 more | 1996-04-16 |
| 5397723 | Process for forming arrayed field effect transistors highly integrated on substrate | Riichiro Shirota, Masaki Momodomi, Seiichi Aritome, Ryouhei Kirisawa, Tetsuro Endoh +1 more | 1995-03-14 |
| 5323039 | Non-volatile semiconductor memory and method of manufacturing the same | Masamichi Asano, Hiroshi Iwahashi, Ryouhei Kirisawa, Satoshi Inoue, Riichiro Shirota +2 more | 1994-06-21 |
| 5179427 | Non-volatile semiconductor memory device with voltage stabilizing electrode | Riichiro Shirota, Yasuo Itoh, Ryouhei Kirisawa, Hideko Odaira, Masaki Momodomi +5 more | 1993-01-12 |
| 4939690 | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation | Masaki Momodomi, Riichiro Shirota, Yasuo Itoh, Satoshi Inoue, Fujio Masuoka +1 more | 1990-07-03 |