PB

Paul R. Besser

AM AMD: 177 patents #8 of 9,279Top 1%
Globalfoundries: 26 patents #104 of 4,424Top 3%
SL Spansion Llc.: 5 patents #175 of 769Top 25%
NV NVIDIA: 4 patents #1,685 of 7,811Top 25%
Lam Research: 3 patents #812 of 2,128Top 40%
IN Intermolecular: 2 patents #139 of 248Top 60%
CL Cerfe Labs: 1 patents #6 of 13Top 50%
AD Adavanced Micro Devices: 1 patents #1 of 13Top 8%
Cypress Semiconductor: 1 patents #1,072 of 1,852Top 60%
📍 Sunnyvale, CA: #13 of 14,302 inventorsTop 1%
🗺 California: #480 of 386,348 inventorsTop 1%
Overall (All Time): #2,943 of 4,157,543Top 1%
212
Patents All Time

Issued Patents All Time

Showing 101–125 of 212 patents

Patent #TitleCo-InventorsDate
6657268 Metal gate stack with etch stop layer having implanted metal species Srikanteswara Dakshina-Murthy 2003-12-02
6656836 Method of performing a two stage anneal in the formation of an alloy interconnect Pin-Chin Connie Wang 2003-12-02
6656834 Method of selectively alloying interconnect regions by deposition process Larry Zhao 2003-12-02
6642590 Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process Qi Xiang, Matthew S. Buynoski 2003-11-04
6633085 Method of selectively alloying interconnect regions by ion implantation Larry Zhao, Donggang D. Wu 2003-10-14
6629879 Method of controlling barrier metal polishing processes based upon X-ray fluorescence measurements Susan Kim 2003-10-07
6617176 METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED John Sanchez, Pin-Chin Connie Wang, Christy Mei-Chu Woo 2003-09-09
6614064 Transistor having a gate stick comprised of a metal, and a method of making same William S. Brennan 2003-09-02
6611576 Automated control of metal thickness during film deposition Paul L. King 2003-08-26
6610594 Locally increasing sidewall density by ion implantation Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Fred Cheung 2003-08-26
6610181 Method of controlling the formation of metal layers Paul L. King, Susan Kim 2003-08-26
6605513 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Eric N. Paton, Ercan Adem, Jacques Bertrand, Matthew S. Buynoski, John Foster +4 more 2003-08-12
6602754 Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer George Jonathan Kluth, Minh Van Ngo 2003-08-05
6602781 Metal silicide gate transistors Qi Xiang, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton 2003-08-05
6589408 Non-planar copper alloy target for plasma vapor deposition systems Pin-Chin Connie Wang, Sergey Lopatin, Minh Quoc Tran 2003-07-08
6589858 Method of making metal gate stack with etch endpoint tracer layer Srikanteswara Dakshina-Murthy 2003-07-08
6589866 Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process Qi Xiang, Matthew S. Buynoski 2003-07-08
6583012 Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes Matthew S. Buynoski, Qi Xiang 2003-06-24
6566252 Method for simultaneous deposition and sputtering of TEOS and device thereby formed Minh Van Ngo 2003-05-20
6562718 Process for forming fully silicided gates Qi Xiang, Ercan Adem, Jacques Bertrand, Matthew S. Buynoski, John Foster +5 more 2003-05-13
6559051 Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors Matthew S. Buynoski, Paul L. King, Eric N. Paton, Qi Xang 2003-05-06
6555479 Method for forming openings for conductive interconnects Frederick N. Hause, Frank Mauersberger, Errol Todd Ryan, William S. Brennan, John A. Iacoponi +1 more 2003-04-29
6545370 Composite silicon nitride sidewall spacers for reduced nickel silicide bridging Minh Van Ngo, Christy Mei-Chu Woo 2003-04-08
6534869 Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby Bryan Tracy, Minh Van Ngo 2003-03-18
6528362 Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process Qi Xiang, Matthew S. Buynoski 2003-03-04