Issued Patents All Time
Showing 76–100 of 212 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6861350 | Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode | Minh Van Ngo, Christy Mei-Chu Woo, Jinsong Yin, James Pan | 2005-03-01 |
| 6861349 | Method of forming an adhesion layer with an element reactive with a barrier layer | Sergey Lopatin, Matthew S. Buynoski, Pin-Chin Connie Wang | 2005-03-01 |
| 6858503 | Depletion to avoid cross contamination | Minh Van Ngo, Ming-Ren Lin, Qi Xiang, Eric N. Paton, Jung-Suk Goo | 2005-02-22 |
| 6835656 | Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation | Minh Van Ngo | 2004-12-28 |
| 6835655 | Method of implanting copper barrier material to improve electrical performance | Matthew S. Buynoski, Sergey Lopatin | 2004-12-28 |
| 6830998 | Gate dielectric quality for replacement metal gate transistors | James Pan, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin | 2004-12-14 |
| 6815340 | Method of forming an electroless nucleation layer on a via bottom | Sergey Lopatin, Matthew S. Buynoski, Pin-Chin Connie Wang | 2004-11-09 |
| 6811448 | Pre-cleaning for silicidation in an SMOS process | Eric N. Paton, Qi Xiang | 2004-11-02 |
| 6809032 | Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques | Frank Mauersberger, Peter J. Beckage, Frederick N. Hause, Errol Todd Ryan, William S. Brennan +1 more | 2004-10-26 |
| 6797614 | Nickel alloy for SMOS process silicidation | Eric N. Paton, Minh Van Ngo, Qi Xiang | 2004-09-28 |
| 6787864 | Mosfets incorporating nickel germanosilicided gate and methods for their formation | Eric N. Paton, Qi Xiang, Ming-Ren Lin, Minh Van Ngo, Haihong Wang | 2004-09-07 |
| 6784506 | Silicide process using high K-dielectrics | Qi Xiang, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2004-08-31 |
| 6773978 | Methods for improved metal gate fabrication | Eric N. Paton, James Pan | 2004-08-10 |
| 6764912 | Passivation of nitride spacer | John Foster, Eric N. Paton, Matthew S. Buynoski, Qi Xiang, Paul L. King | 2004-07-20 |
| 6730576 | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | Haihong Wang, Jung-Suk Goo, Minh Van Ngo, Eric N. Paton, Qi Xiang | 2004-05-04 |
| 6727560 | Engineered metal gate electrode | James Pan, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin | 2004-04-27 |
| 6724087 | Laminated conductive lines and methods of forming the same | Matthew S. Buynoski, Sergey Lopatin, Lu You | 2004-04-20 |
| 6703308 | Method of inserting alloy elements to reduce copper diffusion and bulk diffusion | Matthew S. Buynoski, Sergey Lopatin, Alline F. Myers, Phin-Chin Connie Wang | 2004-03-09 |
| 6703307 | Method of implantation after copper seed deposition | Sergey Lopatin, Matthew S. Buynoski | 2004-03-09 |
| 6689688 | Method and device using silicide contacts for semiconductor processing | Simon S. Chan, David E. Brown, Eric N. Paton | 2004-02-10 |
| 6689689 | Selective deposition process for allowing damascene-type Cu interconnect lines | Darrell M. Erb, Sergey Lopatin | 2004-02-10 |
| 6664604 | Metal gate stack with etch stop layer | Srikanteswara Dakshina-Murthy | 2003-12-16 |
| 6660618 | Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems | Susan H. Chen | 2003-12-09 |
| 6660621 | Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation | Minh Van Ngo | 2003-12-09 |
| 6661067 | Nitrogen-plasma treatment for reduced nickel silicide bridging | Minh Van Ngo, Christy Mei-Chu Woo, Robert A. Huertas | 2003-12-09 |