SC

Susan H. Chen

AM AMD: 21 patents #507 of 9,279Top 6%
Applied Materials: 1 patents #4,780 of 7,310Top 70%
Overall (All Time): #198,619 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6660618 Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Paul R. Besser 2003-12-09
6511904 Reverse mask and nitride layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Paul R. Besser 2003-01-28
6461923 Sidewall spacer etch process for improved silicide formation Angela T. Hui, Paul R. Besser 2002-10-08
6391750 Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness Paul R. Besser 2002-05-21
6383947 Anti-reflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies Paul R. Besser, Bhanwar Singh, Darrell M. Erb, Carmen Morales 2002-05-07
6368949 Post-spacer etch surface treatment for improved silicide formation Simon S. Chan 2002-04-09
6355575 Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern Fei Wang, Simon S. Chan 2002-03-12
6346745 Cu-A1 combined interconnect system Takeshi Nogami 2002-02-12
6331732 Via structure in an integrated circuit utilizing a high conductivity metal interconnect and a method for manufacturing same Subhash Gupta 2001-12-18
6294396 Monitoring barrier metal deposition for metal interconnect Takeshi Nogami, Imran Hashim 2001-09-25
6268285 Method of removing plasma etch damage to pre-silicidized surfaces by wet silicon etch Steven C. Avanzino 2001-07-31
6165855 Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies Paul R. Besser, Bhanwar Singh, Darrell M. Erb, Carmen Morales 2000-12-26
6159863 Insitu hardmask and metal etch in a single etcher Judi Quan Rizzuto, Anne E. Sanderfer 2000-12-12
6140706 Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers Fei Wang, Simon S. Chan 2000-10-31
6117769 Pad structure for copper interconnection and its formation Takeshi Nogami, Shekhar Pramanick 2000-09-12
6114235 Multipurpose cap layer dielectric David K. Foote, Minh Van Ngo, Christopher F. Lyons, Fei Wang, Raymond T. Lee +2 more 2000-09-05
6071824 Method and system for patterning to enhance performance of a metal layer of a semiconductor device Bhanwar Singh, Subhash Gupta, Mutya Vicente 2000-06-06
6054384 Use of hard masks during etching of openings in integrated circuits for high etch selectivity Fei Wang 2000-04-25
5994206 Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method Subhash Gupta 1999-11-30
5726920 Watchdog system having data differentiating means for use in monitoring of semiconductor wafer testing line Ying Shiau, Chern-Jiann Lee 1998-03-10
5468339 Plasma etch process Subhash Gupta 1995-11-21
5468340 Highly selective high aspect ratio oxide etch method and products made by the process Subhash Gupta, Angela T. Hui 1995-11-21