Issued Patents All Time
Showing 26–50 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10181420 | Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias | Jason E. Stephens, David Permana, Guillaume Bouche, Mark A. Zaleski, Anbu Selvam K M Mahalingam +6 more | 2019-01-15 |
| 10056458 | Siloxane and organic-based MOL contact patterning | Chang Ho Maeng, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche, Haifeng Sheng +9 more | 2018-08-21 |
| 10056373 | Transistor contacts self-aligned in two dimensions | Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye +1 more | 2018-08-21 |
| 9960256 | Merged gate and source/drain contacts in a semiconductor device | Guillaume Bouche | 2018-05-01 |
| 9899268 | Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device | Guillaume Bouche | 2018-02-20 |
| 9852984 | Cut first alternative for 2D self-aligned via | Guillaume Bouche, Sudharshanan Raghunathan | 2017-12-26 |
| 9842801 | Self-aligned via and air gap | Mark A. Zaleski | 2017-12-12 |
| 9825031 | Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices | Guillaume Bouche, Jason E. Stephens, David Permana, Jagannathan Vasudevan | 2017-11-21 |
| 9735154 | Semiconductor structure having gap fill dielectric layer disposed between fins | Dae-Han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran | 2017-08-15 |
| 9704973 | Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins | Ruilong Xie | 2017-07-11 |
| 9679805 | Self-aligned back end of line cut | Guillaume Bouche, Mark A. Zaleski | 2017-06-13 |
| 9666717 | Split well zero threshold voltage field effect transistor for integrated circuits | Jagar Singh, Konstantin G. Korablev | 2017-05-30 |
| 9659928 | Semiconductor device having a high-K gate dielectric above an STI region | Roman Boschke, Markus Forsberg | 2017-05-23 |
| 9660040 | Transistor contacts self-aligned two dimensions | Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye +1 more | 2017-05-23 |
| 9660075 | Integrated circuits with dual silicide contacts and methods for fabricating same | Shao-Ming Koh, Guillaume Bouche, Jeremy A. Wahl | 2017-05-23 |
| 9640625 | Self-aligned gate contact formation | Guillaume Bouche, Gabriel Padron Wells, Andre P. Labonte, Jing Wan | 2017-05-02 |
| 9620587 | Three-dimensional electrostatic discharge semiconductor device | Jagar Singh, Mahadeva Iyer Natarajan | 2017-04-11 |
| 9608086 | Metal gate structure and method of formation | Dae Geun Yang, Mariappan Hariharaputhiran, Jing Wan | 2017-03-28 |
| 9601486 | ESD snapback based clamp for finFET | Jagar Singh, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar | 2017-03-21 |
| 9583351 | Inverted contact | — | 2017-02-28 |
| 9520395 | FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack | Guillaume Bouche, Xiang Hu, Jerome F. Wandell, Sandeep Gaan | 2016-12-13 |
| 9515026 | Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark | Jeong Soo Kim, Francis M. Tambwe | 2016-12-06 |
| 9508642 | Self-aligned back end of line cut | Guillaume Bouche, Mark A. Zaleski | 2016-11-29 |
| 9508850 | Epitaxial block layer for a fin field effect transistor device | Zhenyu Hu, Richard J. Carter, Qi Zhang, Sruthi Muralidharan, Amy L. Child | 2016-11-29 |
| 9502293 | Self-aligned via process flow | Guillaume Bouche, Sudharshanan Raghunthathan | 2016-11-22 |