Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12026866 | Method and apparatus for rechecking defective product | Shunan ZHANG, Xuedong Zhang, Hao Su | 2024-07-02 |
| 10714376 | Method of forming semiconductor material in trenches having different widths, and related structures | Chih-Chiang Chang, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu +2 more | 2020-07-14 |
| 10062641 | Integrated circuits including a dummy metal feature and methods of forming the same | Shifeng Zhao, Juan Boon Tan, Soh Yun Siah | 2018-08-28 |
| 10056458 | Siloxane and organic-based MOL contact patterning | Chang Ho Maeng, Andy Wei, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche +9 more | 2018-08-21 |
| 9991363 | Contact etch stop layer with sacrificial polysilicon layer | Haigou Huang, Jinsheng Gao, Jinping Liu, Huy Cao, Hui Zang | 2018-06-05 |
| 9966272 | Methods for nitride planarization using dielectric | Haigou Huang, Tai Fong Chao, Jiehui Shu, Jinping Liu, Xingzhao Shi +1 more | 2018-05-08 |
| 9905472 | Silicon nitride CESL removal without gate cap height loss and resulting device | Jiehui Shu, Jinping Liu | 2018-02-27 |
| 9793208 | Plasma discharge path | Juan Boon Tan, Wanbing Yi, Daxiang Wang, Soh Yun Siah | 2017-10-17 |
| 9761452 | Devices and methods of forming SADP on SRAM and SAQP on logic | Jiehui Shu, Daniel Jaeger, Garo Derderian, Jinping Liu | 2017-09-12 |
| 9711447 | Self-aligned lithographic patterning with variable spacings | Jiehui Shu, Qiang Fang, Daniel W. Fisher, Haigou Huang, Jinping Liu +1 more | 2017-07-18 |
| 9673301 | Methods of forming spacers on FinFET devices | Fuad H. Al-Amoody, Jinping Liu | 2017-06-06 |
| 9627274 | Methods of forming self-aligned contacts on FinFET devices | Xintuo Dai, Jinping Liu, Huang Liu | 2017-04-18 |
| 9147654 | Integrated circuit system employing alternating conductive layers | Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn | 2015-09-29 |
| 8519445 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang +2 more | 2013-08-27 |
| 8183149 | Method of fabricating a conductive interconnect arrangement for a semiconductor device | David Permana, Ravi Prakash Srivastava, Dimitri Kioussis | 2012-05-22 |
| 7993997 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang +2 more | 2011-08-09 |
| 7400030 | Schottky diode with silver layer contacting the ZnO and MgxZn1−xO films | Yicheng Lu, Sriram Muthukumar, Nuri Emanetoglu, Jian Zhong, Shaohua Liang | 2008-07-15 |
| 6846731 | Schottky diode with silver layer contacting the ZnO and MgxZn1-xO films | Yicheng Lu, Sriram Muthukumar, Nuri Emanetoglu, Jian Zhong | 2005-01-25 |