Issued Patents All Time
Showing 76–100 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9691775 | Combined SADP fins for semiconductor devices and methods of making the same | Nicholas V. LiCausi, Eric S. Kozarsky | 2017-06-27 |
| 9679805 | Self-aligned back end of line cut | Andy Wei, Mark A. Zaleski | 2017-06-13 |
| 9679809 | Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines | Jongwook Kye, Yan Wang, Chenchen Jacob Wang, Wenhui Wang, Lei Yuan +1 more | 2017-06-13 |
| 9673316 | Vertical semiconductor device having frontside interconnections | Christopher S. Blair, Albert Bergemont, Sudarsan Uppili, Fanling H. Yang | 2017-06-06 |
| 9666488 | Pass-through contact using silicide | Tuhin Guha Neogi, David Pritchard, Scott Luning, David Doman | 2017-05-30 |
| 9660040 | Transistor contacts self-aligned two dimensions | Andy Wei, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye +1 more | 2017-05-23 |
| 9660075 | Integrated circuits with dual silicide contacts and methods for fabricating same | Shao-Ming Koh, Jeremy A. Wahl, Andy Wei | 2017-05-23 |
| 9640625 | Self-aligned gate contact formation | Andy Wei, Gabriel Padron Wells, Andre P. Labonte, Jing Wan | 2017-05-02 |
| 9589829 | FinFET device including silicon oxycarbon isolation structure | Huy Cao, Daniel Jaeger | 2017-03-07 |
| 9530689 | Methods for fabricating integrated circuits using multi-patterning processes | Deniz E. Civay, Jason E. Stephens, Jiong Li, Richard A. Farrell | 2016-12-27 |
| 9520395 | FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack | Andy Wei, Xiang Hu, Jerome F. Wandell, Sandeep Gaan | 2016-12-13 |
| 9508642 | Self-aligned back end of line cut | Andy Wei, Mark A. Zaleski | 2016-11-29 |
| 9502528 | Borderless contact formation through metal-recess dual cap integration | Jason E. Stephens, Tuhin Guha Neogi, Mark A. Zaleski, Andy Wei | 2016-11-22 |
| 9502293 | Self-aligned via process flow | Andy Wei, Sudharshanan Raghunthathan | 2016-11-22 |
| 9490340 | Methods of forming nanowire devices with doped extension regions and the resulting devices | Shao-Ming Koh, Jing Wan, Andy Wei | 2016-11-08 |
| 9460963 | Self-aligned contacts and methods of fabrication | Gabriel Padron Wells, Xiang Hu, Andre P. Labonte | 2016-10-04 |
| 9461128 | Method for creating self-aligned transistor contacts | Mark A. Zaleski, Andy Wei, Jason E. Stephens, Tuhin Guha Neogi | 2016-10-04 |
| 9455204 | 10 nm alternative N/P doped fin for SSRW scheme | Huy Cao, Jinping Liu, Huang Liu | 2016-09-27 |
| 9450074 | LDMOS with field plate connected to gate | Fanling H. Yang, Timothy K. McGuire, Sudarsan Uppili | 2016-09-20 |
| 9443931 | Fabricating stacked nanowire, field-effect transistors | Hui Zang, Gabriel Padron Wells | 2016-09-13 |
| 9431512 | Methods of forming nanowire devices with spacers and the resulting devices | Shao-Ming Koh, Jing Wan, Andy Wei | 2016-08-30 |
| 9425097 | Cut first alternative for 2D self-aligned via | Andy Wei, Sudharshanan Raghunathan | 2016-08-23 |
| 9412655 | Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines | Jason E. Stephens, Vikrant Chauhan, Andy Wei | 2016-08-09 |
| 9406775 | Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints | Andy Wei, Youngtag Woo | 2016-08-02 |
| 9397004 | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | Erik Geiss, Scott Beasor, Andy Wei, Deniz E. Civay | 2016-07-19 |