Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12169348 | Anti-glare apparatus and mirror having lens assembly with controlled optical axis direction | Junrui Zhang, Ronghua Lan, Hongbo Feng, Xuehui Zhu, Meng Guo +1 more | 2024-12-17 |
| 12111572 | Methods of greytone imprint lithography to fabricate optical devices | Kang Luo, Erica Chen, Yongan Xu | 2024-10-08 |
| 11709423 | Methods of greytone imprint lithography to fabricate optical devices | Kang Luo, Erica Chen, Yongan Xu | 2023-07-25 |
| 11543793 | Developer critical dimension control with pulse development | Richard C. Johnson, Yongan Xu | 2023-01-03 |
| 11508823 | Low capacitance low RC wrap-around-contact | Ruilong Xie, Ekmini Anuja De Silva, Jing Guo, Cheng Chi | 2022-11-22 |
| 11189566 | Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias | Dongbing Shao, Lawrence A. Clevenger, Shyng-Tsong Chen, Jing Sha | 2021-11-30 |
| 11177437 | Alignment through topography on intermediate component for memory device patterning | Michael Rizzolo, Injo Ok, Theodorus E. Standaert | 2021-11-16 |
| 11022890 | Photoresist bridging defect removal by reverse tone weak developer | Zhenxing Bi, Karen E. Petrillo, Nicole Saulnier | 2021-06-01 |
| 11022891 | Photoresist bridging defect removal by reverse tone weak developer | Zhenxing Bi, Karen E. Petrillo, Nicole Saulnier | 2021-06-01 |
| 10978550 | Efficient metal-insulator-metal capacitor | Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann Mignot | 2021-04-13 |
| 10915085 | Developer critical dimension control with pulse development | Richard C. Johnson, Yongan Xu | 2021-02-09 |
| 10879190 | Patterning integration scheme with trench alignment marks | Chih-Chao Yang, Dominik Metzler, Cornelius Brown Peethala | 2020-12-29 |
| 10734281 | Method and structure to fabricate a nanoporous membrane | Zhenxing Bi, Kangguo Cheng, Shogo Mochizuki | 2020-08-04 |
| 10658589 | Alignment through topography on intermediate component for memory device patterning | Michael Rizzolo, Injo Ok, Theodorus E. Standaert | 2020-05-19 |
| 10651266 | Efficient metal-insulator-metal capacitor | Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann Mignot | 2020-05-12 |
| 10534276 | Lithographic photomask alignment using non-planar alignment structures formed on wafer | Chih-Chao Yang, Dominik Metzler, Cornelius Brown Peethala | 2020-01-14 |
| 10461174 | Vertical field effect transistors with self aligned gate and source/drain contacts | Cheng Chi, Ruilong Xie | 2019-10-29 |
| 10256289 | Efficient metal-insulator-metal capacitor fabrication | Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann Mignot | 2019-04-09 |
| 10222919 | Capacitive touch screen and single layer wiring electrode array | Taiyi Cheng, Tianming Zhao | 2019-03-05 |
| 10224246 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Kangguo Cheng, Peng Xu | 2019-03-05 |
| 10217658 | Method and structure for minimizing fin reveal variation in FinFET transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-02-26 |
| 10090378 | Efficient metal-insulator-metal capacitor | Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann Mignot | 2018-10-02 |
| 10020221 | Method and structure for minimizing fin reveal variation in FinFET transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-07-10 |
| 9941150 | Method and structure for minimizing fin reveal variation in FinFET transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-04-10 |
| 9805983 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Kangguo Cheng, Peng Xu | 2017-10-31 |