Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7456450 | CMOS devices with hybrid channel orientations and method for fabricating the same | Xiangdong Chen, James J. Toomey, Haining Yang | 2008-11-25 |
| 7452758 | Process for making FinFET device with body contact and buried oxide junction isolation | Haining Yang | 2008-11-18 |
| 7442586 | SOI substrate and SOI device, and method for forming the same | Zhijiong Luo | 2008-10-28 |
| 7442614 | Silicon on insulator devices having body-tied-to-source and methods of making | Jack A. Mandelman, Keith Kwong Hon Wong, Chih-Chao Yang, Haining Yang | 2008-10-28 |
| 7436030 | Strained MOSFETs on separated silicon layers | Haining Yang, Wai-Kin Li | 2008-10-14 |
| 7393746 | Post-silicide spacer removal | Sunfei Fang, Jiang Yan, Siddhartha Panda, Yong Meng Lee, Junjung Kim | 2008-07-01 |
| 7390745 | Pattern enhancement by crystallographic etching | Kenneth T. Settlemyer, Jr., James J. Toomey, Haining Yang | 2008-06-24 |
| 7122437 | Deep trench capacitor with buried plate electrode and isolation collar | Chun-Yung Sung, Ravikumar Ramachandran, Ramachandra Divakaruni, Carl Radens | 2006-10-17 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices | Haining Yang | 2006-09-05 |
| 7023041 | Trench capacitor vertical structure | Giuseppe La Rosa, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens, Alvin W. Strong | 2006-04-04 |
| 6936511 | Inverted buried strap structure and method for vertical transistor DRAM | Ramachandra Divakaruni | 2005-08-30 |
| 6897107 | Method for forming TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Rajeev Malik, Jack A. Mandelman, Venkatachajam C. Jaiprakash | 2005-05-24 |
| 6887761 | Vertical semiconductor devices | Hiroyuki Akatsu, Ravikumar Ramachandran, Kenneth T. Settlemyer, Jr. | 2005-05-03 |
| 6809368 | TTO nitride liner for improved collar protection and TTO reliability | Rama Divakaruni, Rajeev Malik, Jack A. Mandelman, Venkatachalam C. Jaiprakash | 2004-10-26 |
| 6794242 | Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts | Andreas Knorr, Laertis Economikos, Scott D. Halle, Rajeev Malik, Norbert Arnod | 2004-09-21 |
| 6747306 | Vertical gate conductor with buried contact layer for increased contact landing area | — | 2004-06-08 |
| 6548344 | Spacer formation process using oxide shield | Jochen Beintner, Stephan Kudelka | 2003-04-15 |
| 6518616 | Vertical gate top engineering for improved GC and CB process windows | Stephan Kudelka, Venkatachaiam C. Jaiprakash, Carl Radens | 2003-02-11 |
| 6335248 | Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technology | Jack A. Mandelman | 2002-01-01 |