Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7989357 | Method of patterning semiconductor structure and structure thereof | James J. Toomey | 2011-08-02 |
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions | Xiangdong Chen, Haining Yang | 2011-06-28 |
| 7964910 | Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure | — | 2011-06-21 |
| 7955940 | Silicon-on-insulator substrate with built-in substrate junction | Junedong Lee, Dominic J. Schepis | 2011-06-07 |
| 7943474 | EDRAM including metal plates | Keith Kwong Hon Wong, Mahender Kumar | 2011-05-17 |
| 7923365 | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon | Jun Jung Kim, Sang-Jine Park, Min Ho Lee, Sunfei Fang, O-Sung Kwon +1 more | 2011-04-12 |
| 7911001 | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices | Kyoung-Woo Lee, Ja-Hum Ku, Taehoon Lee, Seung-Man Choi | 2011-03-22 |
| 7910451 | Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor | — | 2011-03-22 |
| 7906384 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | — | 2011-03-15 |
| 7884448 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Haining Yang | 2011-02-08 |
| 7868461 | Embedded interconnects, and methods for forming same | Haining Yang | 2011-01-11 |
| 7863693 | Forming conductive stud for semiconductive devices | Sunfei Fang, Jiang Yan | 2011-01-04 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Xiangdong Chen, Geng Wang, Haining Yang | 2011-01-04 |
| 7847357 | High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same | Bruce B. Doris, David R. Medeiros, Anna W. Topol | 2010-12-07 |
| 7842592 | Channel strain engineering in field-effect-transistor | Rajendran Krishnasamy, Jin-Ping Han, Ernst Demm | 2010-11-30 |
| 7816231 | Device structures including backside contacts, and methods for forming same | Haining Yang | 2010-10-19 |
| 7808082 | Structure and method for dual surface orientations for CMOS transistors | Haining Yang, Keith Kwong Hon Wong, Chih-Chao Yang | 2010-10-05 |
| 7790622 | Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes | Kyoung-Woo Lee, Ja-Hum Ku, Jun Jung Kim, Chong-Kwang Chang, Min-Chul Sun +1 more | 2010-09-07 |
| 7790542 | CMOS devices having reduced threshold voltage variations and methods of manufacture thereof | Haining Yang | 2010-09-07 |
| 7772095 | Integrated circuit having localized embedded SiGe and method of manufacturing | — | 2010-08-10 |
| 7749903 | Gate patterning scheme with self aligned independent gate etch | Scott D. Halle, Matthew E. Colburn, Bruce B. Doris | 2010-07-06 |
| 7750429 | Self-aligned and extended inter-well isolation structure | Zhijiong Luo, Haining Yang | 2010-07-06 |
| 7741188 | Deep trench (DT) metal-insulator-metal (MIM) capacitor | Eduard A. Cartier, Michael P. Chudzik, Naim Moumen | 2010-06-22 |
| 7736966 | CMOS devices with hybrid channel orientations and method for fabricating the same | Xiangdong Chen, James J. Toomey, Haining Yang | 2010-06-15 |
| 7728364 | Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation | Huilong Zhu | 2010-06-01 |