Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7445978 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2008-11-04 |
| 7442611 | Method of applying stresses to PFET and NFET transistor channels for improved performance | Victor Chan, Haining Yang | 2008-10-28 |
| 7396724 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals | Victor Chan, Haining Yang, Eng Hua Lim | 2008-07-08 |
| 7393746 | Post-silicide spacer removal | Thomas W. Dyer, Sunfei Fang, Jiang Yan, Siddhartha Panda, Junjung Kim | 2008-07-01 |
| 7309637 | Method to enhance device performance with selective stress relief | Haining Yang, Victor Chan | 2007-12-18 |
| 7256084 | Composite stress spacer | Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Liang-Choo Hsia, Young Way Teh +3 more | 2007-08-14 |
| 7193254 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance | Victor Chan, Haining Yang | 2007-03-20 |
| 7141854 | Double-gated silicon-on-insulator (SOI) transistors with corner rounding | Da Jin, David Vigar | 2006-11-28 |
| 6927104 | Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding | Da Jin, David Vigar | 2005-08-09 |
| 6835609 | Method of forming double-gate semiconductor-on-insulator (SOI) transistors | Da Jin, Mau Lam Lai, David Vigar, Siow Lee Chwa | 2004-12-28 |
| 6787404 | Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance | Da Jin, David Vigar | 2004-09-07 |
| 6583011 | Method for forming damascene dual gate for improved oxide uniformity and control | Li-Qun Xia, Gao Feng | 2003-06-24 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yang Pan, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2003-01-28 |
| 6436754 | Selective salicide process by reformation of silicon nitride sidewall spacers | — | 2002-08-20 |
| 6372569 | Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance | Gao Feng, Yunqzang Zhang, Ravi Sundaresan | 2002-04-16 |
| 6258648 | Selective salicide process by reformation of silicon nitride sidewall spacers | — | 2001-07-10 |
| 6107140 | Method of patterning gate electrode conductor with ultra-thin gate oxide | Yunqiang Zhang | 2000-08-22 |
| 6025267 | Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices | Kin Leong Pey, Soh Yun Siah | 2000-02-15 |