Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10854472 | Method for forming a metal gate including de-oxidation of an oxidized surface of the metal gate utilizing a reducing agent | Huang Liu, Jean-Baptiste Laloe | 2020-12-01 |
| 10290634 | Multiple threshold voltages using fin pitch and profile | Min-hwa Chi | 2019-05-14 |
| 9905673 | Stress memorization and defect suppression techniques for NMOS transistor devices | Min-hwa Chi | 2018-02-27 |
| 9711619 | Stress memorization and defect suppression techniques for NMOS transistor devices | Min-hwa Chi | 2017-07-18 |
| 9704759 | Methods of forming CMOS based integrated circuit products using disposable spacers | Min-hwa Chi, Garo Derderian | 2017-07-11 |
| 9607989 | Forming self-aligned NiSi placement with improved performance and yield | Xusheng Wu, Yue Hu, Xin-Yong WANG, Yong Meng Lee, Lun Zhao +1 more | 2017-03-28 |
| 9396995 | MOL contact metallization scheme for improved yield and device reliability | Suraj K. Patil, Min-hwa Chi, Garo Derderian | 2016-07-19 |
| 9385124 | Methods of forming reduced thickness spacers in CMOS based integrated circuit products | Min-hwa Chi, Garo Derderian | 2016-07-05 |
| 9385030 | Spacer to prevent source-drain contact encroachment | Yong Meng Lee, Yue Hu | 2016-07-05 |
| 9184288 | Semiconductor structures with bridging films and methods of fabrication | Sipeng Gu, Zhiguo Sun, Sandeep Gaan, Danni Chen, Huang Liu | 2015-11-10 |
| 9123783 | Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection | Xin-Yong WANG, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo +2 more | 2015-09-01 |