Issued Patents All Time
Showing 26–50 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9418832 | Method of forming a dielectric film | Hung-Wei Liu, Tsung-Liang Chen, Zhiguo Sun | 2016-08-16 |
| 9401416 | Method for reducing gate height variation due to overlapping masks | Hong Yu, Jin Ping Liu, Haigou Huang | 2016-07-26 |
| 9385192 | Shallow trench isolation integration methods and devices formed thereby | Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong +6 more | 2016-07-05 |
| 9368342 | Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch | Haigou Huang, Jin Ping Liu | 2016-06-14 |
| 9349635 | Integrated circuits and methods of forming the same with multi-level electrical connection | San Leong Liew | 2016-05-24 |
| 9329471 | Achieving a critical dimension target based on resist characteristics | Guoxiang Ning, Xintuo Dai, Chin Teong Lim | 2016-05-03 |
| 9324841 | Methods for preventing oxidation damage during FinFET fabrication | Hong Yu, Hyucksoo Yang, Richard J. Carter | 2016-04-26 |
| 9318440 | Formation of carbon-rich contact liner material | Huy Cao, Songkram Srivathanakul, Garo Derderian, Boaz Alperson | 2016-04-19 |
| 9305832 | Dimension-controlled via formation processing | Xiang Hu, Yuping Ren, Duohui Bei, Sipeng Gu | 2016-04-05 |
| 9275898 | Method to improve selectivity cobalt cap process | Jiehui Shu, Zhiguo Sun, Yang Bum Lee | 2016-03-01 |
| 9230886 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Alex See, Hai Cong, Xuesong Rao +1 more | 2016-01-05 |
| 9230863 | Method for producing integrated circuit with smaller grains of tungsten | Jialin Yu, Jilin Xia, Girish Bohra | 2016-01-05 |
| 9230822 | Uniform gate height for mixed-type non-planar semiconductor devices | Hong Yu, Haigou Huang, Jin Ping Liu | 2016-01-05 |
| 9184288 | Semiconductor structures with bridging films and methods of fabrication | Sipeng Gu, Zhiguo Sun, Sandeep Gaan, Danni Chen, Wen-Pin Peng | 2015-11-10 |
| 9153693 | FinFET gate with insulated vias and method of making same | Hong Yu, Wang Zheng, Yongsik Moon | 2015-10-06 |
| 9142422 | Methods of fabricating defect-free semiconductor structures | Hung-Wei Liu, Zhiguo Sun, Jin Ping Liu | 2015-09-22 |
| 9130019 | Formation of carbon-rich contact liner material | Huy Cao, Songkram Srivathanakul, Garo Derderian, Boaz Alperson | 2015-09-08 |
| 9123771 | Shallow trench isolation integration methods and devices formed thereby | Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong +6 more | 2015-09-01 |
| 9093561 | Modified, etch-resistant gate structure(s) facilitating circuit fabrication | Hong Yu, Lun Zhao, Richard J. Carter | 2015-07-28 |
| 9087870 | Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same | Wei Tong, Hongliang Shen, Jin Ping Liu, Seung Kim | 2015-07-21 |
| 8993446 | Method of forming a dielectric film | Hung-Wei Liu, Tsung-Liang Chen, Zhiguo Sun | 2015-03-31 |
| 8987134 | Reliable interconnect for semiconductor device | Zhehui Wang, Kwee Liang Yeo, Hai Cong, Wen-Zhan Zhou | 2015-03-24 |
| 8962474 | Method for forming an air gap around a through-silicon via | Hong Yu | 2015-02-24 |
| 8962407 | Method and device to achieve self-stop and precise gate height | Hong Yu, Wang Haiting, Yongsik Moon, James Lee | 2015-02-24 |
| 8940650 | Methods for fabricating integrated circuits utilizing silicon nitride layers | Huy Cao, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan | 2015-01-27 |