Issued Patents All Time
Showing 51–75 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8940637 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Alex See, Hai Cong, Xuesong Rao +1 more | 2015-01-27 |
| 8916939 | Reliable contacts | Hong Yu | 2014-12-23 |
| 8883634 | Package interconnects | Hong Yu | 2014-11-11 |
| 8877637 | Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacks | Hong Yu | 2014-11-04 |
| 8859417 | Gate electrode(s) and contact structure(s), and methods of fabrication thereof | Jialin Yu, Jilin Xia | 2014-10-14 |
| 8852968 | STI CMP under polish monitoring | Liang Li, Zheng Zou, Alex See | 2014-10-07 |
| 8836139 | CD control | Zheng Zou, Alex See, Hai Cong | 2014-09-16 |
| 8803254 | Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures | Jean-Baptiste Laloe, Wonwoo Kim | 2014-08-12 |
| 8722485 | Integrated circuits having replacement gate structures and methods for fabricating the same | Wei Tong, Yiqun Liu, Tae Hoon Kim, Seung Kim, Haiting Wang | 2014-05-13 |
| 8716150 | Method of forming a low-K dielectric film | Zhiguo Sun, Songkram Srivathanakul, Hung-Wei Liu | 2014-05-06 |
| 8569173 | Methods of protecting elevated polysilicon structures during etching processes | Liang Li, Alex See, Soh Yun Siah, Xue Song Rao, Peng Zhou | 2013-10-29 |
| 8518775 | Integration of eNVM, RMG, and HKMG modules | Alex See, Hai Cong, Zheng Zou | 2013-08-27 |
| 8519482 | Reliable contacts | Hong Yu | 2013-08-27 |
| 8492236 | Step-like spacer profile | Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See +3 more | 2013-07-23 |
| 8405222 | Integrated circuit system with via and method of manufacture thereof | Hong Yu, Feng Zhao, Meisheng Zhou, Liang-Choo Hsia | 2013-03-26 |
| 8354347 | Method of forming high-k dielectric stop layer for contact hole opening | Jianhui Ye, Alex See, Wei Lu, Chun Hui Low, Chim Seng Seet +2 more | 2013-01-15 |
| 8178417 | Method of forming shallow trench isolation structures for integrated circuits | Shailendra Mishra, James Yong Meng Lee, Zhao Lun, Wen Zhi Gao, Chung Woh Lai +2 more | 2012-05-15 |
| 8143651 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2012-03-27 |
| 8013372 | Integrated circuit including a stressed dielectric layer with stable stress | Jeff Shu, Luona Goh, Wei Lu | 2011-09-06 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Alex See, Wei Lu, Hai Cong, Hui Peng Koh +2 more | 2011-06-14 |
| 7892900 | Integrated circuit system employing sacrificial spacers | Wei Lu, Hai Cong, Alex See, Hui Peng Koh, Meisheng Zhou | 2011-02-22 |
| 7855143 | Interconnect capping layer and method of fabrication | Bangun Indajang, Wei Lu | 2010-12-21 |
| 7829422 | Integrated circuit having ultralow-K dielectric layer | Johnny Widodo, Sin Leng Lim | 2010-11-09 |
| 7795680 | Integrated circuit system employing selective epitaxial growth technology | Alex See, James Yong Meng Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao +3 more | 2010-09-14 |
| 7767577 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2010-08-03 |