Issued Patents All Time
Showing 26–50 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7005716 | Dual metal gate process: metals and their silicides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2006-02-28 |
| 6987321 | Copper diffusion deterrent interface | Simon Chooi, Yakub Aliyu, John Sudijono, Subbash Gupta, Sudipto Ranendra Roy +2 more | 2006-01-17 |
| 6967162 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding | Simon Chooi, Yakub Aliyu, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2005-11-22 |
| 6891233 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2005-05-10 |
| 6875285 | System and method for dampening high pressure impact on porous materials | Ching-Ya Wang, Ping Chuang, Yu-Liang Lin, Henry Lo | 2005-04-05 |
| 6846899 | Poly(arylene ether) dielectrics | Christopher Lim, Siu Choon Ng, Hardy Chan, Simon Chooi | 2005-01-25 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2005-01-11 |
| 6835989 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2004-12-28 |
| 6828082 | Method to pattern small features by using a re-flowable hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2004-12-07 |
| 6813796 | Apparatus and methods to clean copper contamination on wafer edge | Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu +2 more | 2004-11-09 |
| 6750519 | Dual metal gate process: metals and their silicides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2004-06-15 |
| 6740580 | Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier | Subhash Gupta, Chyi S. Chern | 2004-05-25 |
| 6730591 | Method of using silicon rich carbide as a barrier material for fluorinated materials | Licheng M. Han, Xu Yi, Simon Chooi, Joseph Xie | 2004-05-04 |
| 6720204 | Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding | John Sudijono, Yakub Aliyu, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2004-04-13 |
| 6705512 | Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding | Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, John Sudijono +2 more | 2004-03-16 |
| 6692579 | Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence | Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, John Sudijono +2 more | 2004-02-17 |
| 6690091 | Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer | Simon Chooi, Yi Xu | 2004-02-10 |
| 6683002 | Method to create a copper diffusion deterrent interface | Simon Chooi, Yakub Aliyu, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2004-01-27 |
| 6677652 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2004-01-13 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-12-16 |
| 6656643 | Method of extreme ultraviolet mask engineering | Subhash Gupta | 2003-12-02 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-10-14 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-08-26 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-08-26 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Elgin Quek | 2003-08-12 |