Issued Patents All Time
Showing 51–75 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6565664 | Method for stripping copper in damascene interconnects | Subhash Gupta, Simon Chooi, Paul Ho | 2003-05-20 |
| 6566260 | Non-metallic barrier formations for copper damascene type interconnects | Simon Chooi, Subhash Gupta, Sangki Hong | 2003-05-20 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2003-04-08 |
| 6540841 | Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate | Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu +2 more | 2003-04-01 |
| 6534393 | Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity | Vijai Kumar Chhagan, Jian Xun Li | 2003-03-18 |
| 6531390 | Non-metallic barrier formations for copper damascene type interconnects | Simon Chooi, Subhash Gupta, Sangki Hong | 2003-03-11 |
| 6530380 | Method for selective oxide etching in pre-metal deposition | Vincent Sih, Simon Chooi, Zainab Ismail, Ping Yu Ee, Sang Yee Loong | 2003-03-11 |
| 6524963 | Method to improve etching of organic-based, low dielectric constant materials | Simon Chooi, Jian Xun Li | 2003-02-25 |
| 6524910 | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers | Wenhe Lin, Kin Leong Pey, Zhong Dong, Simon Chooi | 2003-02-25 |
| 6521539 | Selective etch method for selectively etching a multi-layer stack layer | Xue Chun Dai, Chiew Wah Yap | 2003-02-18 |
| 6489233 | Non-metallic barrier formations for copper damascene type interconnects | Simon Chooi, Subhash Gupta, Sangki Hong | 2002-12-03 |
| 6486080 | Method to form zirconium oxide and hafnium oxide for high dielectric constant materials | Simon Chooi, Wenhe Lin | 2002-11-26 |
| 6479383 | Method for selective removal of unreacted metal after silicidation | Simon Chooi | 2002-11-12 |
| 6475908 | Dual metal gate process: metals and their silicides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2002-11-05 |
| 6475810 | Method of manufacturing embedded organic stop layer for dual damascene patterning | John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu +2 more | 2002-11-05 |
| 6468851 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek +1 more | 2002-10-22 |
| 6465888 | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene | Simon Chooi, Subhash Gupta, Sang-Ki Hong | 2002-10-15 |
| 6465157 | Dual layer pattern formation method for dual damascene interconnect | Jianxun Li, Subhash Gupta, Ming hui Far | 2002-10-15 |
| 6461969 | Multiple-step plasma etching process for silicon nitride | Pei Ching Lee, Wen-Jun Liu | 2002-10-08 |
| 6458695 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Wenhe Lin, Kin Leong Pey, Simon Chooi | 2002-10-01 |
| 6451706 | Attenuation of reflecting lights by surface treatment | Ron Fu Chu, Yang Pan, Qun Ying Lin | 2002-09-17 |
| 6436824 | Low dielectric constant materials for copper damascene | Simon Chooi, Yi Xu | 2002-08-20 |
| 6429129 | Method of using silicon rich carbide as a barrier material for fluorinated materials | Licheng M. Han, Xu Yi, Simon Chooi, Joseph Xie | 2002-08-06 |
| 6429122 | Non metallic barrier formations for copper damascene type interconnects | Simon Chooi, Subhash Gupta, Sangki Hong | 2002-08-06 |
| 6429117 | Method to create copper traps by modifying treatment on the dielectrics surface | John Sudijono, Yakub Aliyu, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy +2 more | 2002-08-06 |