Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211389 | Memory device | Fansheng Kung | 2021-12-28 |
| 10868022 | Flash memory device and fabrication method thereof | Liang Chen, Chao Zhou, Xiao Bo Li | 2020-12-15 |
| 10741610 | Memory cells and memory array structures including RRAM, and fabrication methods thereof | Heng Cao | 2020-08-11 |
| 10615224 | Memory cell, memory cell array and operating method thereof | Heng Cao | 2020-04-07 |
| 10572380 | Structures of bottom select transistor for embedding 3D-NAND in BEOL and methods | Shan Li, Min-hwa Chi | 2020-02-25 |
| 10483283 | Flash memory device and manufacture thereof | Shan Li, Min-hwa Chi | 2019-11-19 |
| 10460803 | Memory cell, memory cell array, memory device and operation method of memory cell array | Heng Cao | 2019-10-29 |
| 10325810 | Memory and fabrication method thereof | Liang Han, Liang Chen | 2019-06-18 |
| 10325916 | Memory device and method for forming the same | Fansheng Kung | 2019-06-18 |
| 10297609 | Flash memory device and manufacture thereof | Shan Li, Min-hwa Chi | 2019-05-21 |
| 10177162 | Semiconductor memory device | Guan Hua Li, Hae Wan Yang | 2019-01-08 |
| 9922985 | Semiconductor memory device and fabrication method thereof | Guan Hua Li, Hae Wan Yang | 2018-03-20 |
| 9640432 | Memory device structure and fabricating method thereof | Jinshuang Zhang, Shaobin Li | 2017-05-02 |
| 6630397 | Method to improve surface uniformity of a layer of arc used for the creation of contact plugs | Jackie Ding, Chi-Long Chung | 2003-10-07 |
| 6459151 | Structure and process of via chain for misalignment test | Chi-Long Chung, Eddie Chiu, Chun-Lin Chen | 2002-10-01 |
| 6444524 | Method for forming a trench capacitor | Jesse Chung, Hsiao-Lei Wang | 2002-09-03 |
| 6391706 | Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate | Chao-Chueh Wu, Jesse Chung, Hsiao-Lei Wang | 2002-05-21 |
| 6187650 | Method for improving global planarization uniformity of a silicon nitride layer used in the formation of trenches by using a sandwich stop layer | Joseph Wu, J. S. Shiao | 2001-02-13 |