Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369389 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Yung-Chen Chien, Jung-Chan Yang +1 more | 2025-07-22 |
| 12210811 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Li-Chung Hsu | 2025-01-28 |
| 12175180 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Jerry Chang Jui Kao, Chung-Hsing Wang | 2024-12-24 |
| 12074069 | Semiconductor device and integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Yung-Chen Chien, Jung-Chan Yang +1 more | 2024-08-27 |
| 11853676 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Li-Chung Hsu | 2023-12-26 |
| 11816413 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Jerry Chang Jui Kao, Chung-Hsing Wang | 2023-11-14 |
| 11791213 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Yung-Chen Chien, Jung-Chan Yang +1 more | 2023-10-17 |
| 11783106 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Li-Chung Hsu | 2023-10-10 |
| 11531802 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Jerry Chang Jui Kao, Li-Chung Hsu | 2022-12-20 |
| 11355395 | Integrated circuit in hybrid row height structure | Jerry Chang Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Yung-Chen Chien, Jung-Chan Yang +1 more | 2022-06-07 |
| 11068637 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Jerry Chang Jui Kao, Chung-Hsing Wang | 2021-07-20 |
| 11003820 | Method of determining a worst case in timing analysis | Ravi Babu Pittu, Li-Chung Hsu, Chung-Hsing Wang | 2021-05-11 |
| 10977402 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Li-Chung Hsu | 2021-04-13 |
| 10776545 | Method of determing a worst case in timing analysis | Ravi Babu Pittu, Li-Chung Hsu, Chung-Hsing Wang | 2020-09-15 |
| 10747924 | Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effect | Ravi Babu Pittu, Li-Chung Hsu, Chung-Hsing Wang | 2020-08-18 |
| 10503849 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Chung-Hsing Wang, Li-Chung Hsu | 2019-12-10 |
| 10176284 | Semiconductor circuit design and manufacture method | Li-Chung Hsu, Tai-Yu Cheng, King-Ho Tam, Yen-Pin Chen, Chung-Hsing Wang | 2019-01-08 |
| 8826212 | Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed | Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam, Yuan-Te Hou +1 more | 2014-09-02 |