Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11783106 | Circuit testing and manufacture using multiple timing libraries | Chung-Hsing Wang, Sung-Yen Yeh, Li-Chung Hsu | 2023-10-10 |
| 11003820 | Method of determining a worst case in timing analysis | Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang | 2021-05-11 |
| 10977402 | Circuit testing and manufacture using multiple timing libraries | Chung-Hsing Wang, Sung-Yen Yeh, Li-Chung Hsu | 2021-04-13 |
| 10776545 | Method of determing a worst case in timing analysis | Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang | 2020-09-15 |
| 10747924 | Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effect | Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang | 2020-08-18 |
| 10503849 | Circuit testing and manufacture using multiple timing libraries | Chung-Hsing Wang, Sung-Yen Yeh, Li-Chung Hsu | 2019-12-10 |