Issued Patents All Time
Showing 51–75 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11552068 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2023-01-10 |
| 11532562 | Routing structure and method of forming the same | Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang | 2022-12-20 |
| 11501052 | Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing | Sheng-Hsiung Chen, Huang-Yu Chen, Jerry Chang Jui Kao | 2022-11-15 |
| 11437319 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2022-09-06 |
| 11366951 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2022-06-21 |
| 11347922 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2022-05-31 |
| 11282829 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Yi-Kan Cheng | 2022-03-22 |
| 11251124 | Power grid structures and method of forming the same | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin | 2022-02-15 |
| 11239154 | Fishbone structure enhancing spacing with adjacent conductive line in power network | Chien-Ju Chao, Fang-Yu Fan, Yi-Chuin Tsai, Kuo-Nan Yang | 2022-02-01 |
| 11227093 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2022-01-18 |
| 11211327 | Via sizing for IR drop reduction | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2021-12-28 |
| 11205032 | Integrated circuit design method, system and computer program product | Chin-Shen Lin, Kuo-Nan Yang, Hiranmay Biswas | 2021-12-21 |
| 11182527 | Cell placement site optimization | Yen-Hung Lin, Yuan-Te Hou | 2021-11-23 |
| 11176305 | Method and system for sigma-based timing optimization | Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu | 2021-11-16 |
| 11176303 | Constrained cell placement | Yen-Hung Lin, Yuan-Te Hou | 2021-11-16 |
| 11157677 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Kuo-Nan Yang, Yi-Kan Cheng | 2021-10-26 |
| 11113443 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Yung-Chin Hou | 2021-09-07 |
| 11087063 | Method of generating layout diagram including dummy pattern conversion and system of generating same | Ritesh Kumar, Kuo-Nan Yang, Hiranmay Biswas, Shu-Yi Ying | 2021-08-10 |
| 11068638 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Kuo-Nan Yang | 2021-07-20 |
| 11068637 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao | 2021-07-20 |
| 11055466 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2021-07-06 |
| 11030381 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou | 2021-06-08 |
| 11017146 | Integrated circuit and method of forming the same | John Lin, Chin-Shen Lin, Kuo-Nan Yang | 2021-05-25 |
| 11003820 | Method of determining a worst case in timing analysis | Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh | 2021-05-11 |
| 10997347 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang | 2021-05-04 |