Issued Patents All Time
Showing 76–100 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10990741 | Multiple patterning method and system for implementing the method | Yen-Hung Lin, Yuan-Te Hou | 2021-04-27 |
| 10977402 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Sung-Yen Yeh, Li-Chung Hsu | 2021-04-13 |
| 10977415 | Integrated device and method of forming the same | Hiranmay Biswas, Kuo-Nan Yang, Meng-Xiang Lee | 2021-04-13 |
| 10964685 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2021-03-30 |
| 10956647 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2021-03-23 |
| 10956643 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Yuan-Te Hou | 2021-03-23 |
| 10943045 | Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2021-03-09 |
| 10936785 | Inter-cell leakage-reducing method of generating layout diagram and system for same | Hiranmay Biswas, Kuo-Nan Yang, Jia Han LIN | 2021-03-02 |
| 10922470 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2021-02-16 |
| 10878157 | Variant cell height integrated circuit design | Yen-Hung Lin, Yuan-Te Hou | 2020-12-29 |
| 10878163 | Semiconductor device including PG-aligned cells and method of generating layout of same | Hiranmay Biswas, Kuo-Nan Yang | 2020-12-29 |
| 10877370 | Stretchable layout design for EUV defect mitigation | Hsing-Lin Yang, Chin-Chang Hsu, Yen-Hung Lin, Wen-Ju Yang | 2020-12-29 |
| 10867916 | Via sizing for IR drop reduction | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2020-12-15 |
| 10867103 | Method and system for forming conductive grid of integrated circuit | Hiranmay Biswas, Kuo-Nan Yang | 2020-12-15 |
| 10804200 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2020-10-13 |
| 10776545 | Method of determing a worst case in timing analysis | Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh | 2020-09-15 |
| 10747924 | Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effect | Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh | 2020-08-18 |
| 10726174 | System and method for simulating reliability of circuit design | Chin-Shen Lin, Meng-Xiang Lee, Kuo-Nan Yang | 2020-07-28 |
| 10678990 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Yi-Kan Cheng, Kumar Lalgudi | 2020-06-09 |
| 10678989 | Method and system for sigma-based timing optimization | Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu | 2020-06-09 |
| 10672709 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Kuo-Nan Yang | 2020-06-02 |
| 10671788 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Yuan-Te Hou | 2020-06-02 |
| 10664641 | Integrated device and method of forming the same | Hiranmay Biswas, Kuo-Nan Yang, Meng-Xiang Lee | 2020-05-26 |
| 10643986 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2020-05-05 |
| 10642949 | Cell placement site optimization | Yen-Hung Lin, Yuan-Te Hou | 2020-05-05 |