Issued Patents All Time
Showing 126–150 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9893009 | Duplicate layering and routing | Huang-Yu Chen, Chi-Yeh Yu | 2018-02-13 |
| 9852989 | Power grid of integrated circuit | Chin-Shen Lin, Min-Yuan Tsai, Kuo-Nan Yang | 2017-12-26 |
| 9799639 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2017-10-24 |
| 9672315 | Optimization for circuit migration | Lee-Chung Lu, Yi-Kan Cheng, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2017-06-06 |
| 9659133 | Method, system and computer program product for generating layout for semiconductor device | Yen-Hung Lin, Chi Wei Hu, Yuan-Te Hou, Chin-Chou Liu | 2017-05-23 |
| 9608604 | Voltage level shifter with single well voltage | Lee-Chung Lu, Chun-Hui Tai, Li-Chun Tien, Shun Li Chen | 2017-03-28 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai +1 more | 2017-03-07 |
| 9563734 | Characterizing cell using input waveform generation considering different circuit topologies | King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen | 2017-02-07 |
| 9564896 | Post-silicon tuning in voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Kuo-Nan Yang | 2017-02-07 |
| 9509301 | Voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, King-Ho Tam +1 more | 2016-11-29 |
| 9501602 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin +1 more | 2016-11-22 |
| 9477803 | Method of generating techfile having reduced corner variation value | King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2016-10-25 |
| 9471738 | Method and apparatus for capacitance extraction | Chih-Cheng Chou, Tsung-Han Wu, Ke-Ying Su, Hsien-Hsin Sean Lee | 2016-10-18 |
| 9436793 | Tier based layer promotion and demotion | Yen-Hung Lin, Chi Wei Hu, Yuan-Te Hou, Chin-Chou Liu | 2016-09-06 |
| 9405880 | Semiconductor arrangement formation | Yen-Hung Lin, Chi Wei Hu, Yuan-Te Hou, Chin-Chou Liu | 2016-08-02 |
| 9400866 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam | 2016-07-26 |
| 9384307 | Stitch and trim methods for double patterning compliant standard cell design | Chin-Hsiung Hsu, Huang-Yu Chen | 2016-07-05 |
| 9367660 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chien-Ju Chao +1 more | 2016-06-14 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Yi-Kan Cheng | 2016-04-19 |
| 9317647 | Method of designing a circuit and system for implementing the method | Shyh-Horng Yang, Chung-Kai Lin, Kuo-Nan Yang, Shou-En Liu, Jhong-Sheng Wang +1 more | 2016-04-19 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | Jerry Chang Jui Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu +1 more | 2016-04-12 |
| 9287257 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2016-03-15 |
| 9275186 | Optimization for circuit migration | Lee-Chung Lu, Yi-Kan Cheng, Chen-Fu Huang, Hsiao-Shu Chao, Chin-Yu Chiang +3 more | 2016-03-01 |
| 9262573 | Cell having shifted boundary and boundary-shift scheme | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2016-02-16 |
| 9223922 | Semiconductor device design method | Ping-Hung Yuh, Cheng-I Huang | 2015-12-29 |