Issued Patents All Time
Showing 151–175 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang +2 more | 2015-12-15 |
| 9201107 | Cell characterization with Miller capacitance | Nitesh Katta, Jerry Chang Jui Kao, King-Ho Tam, Kuo-Nan Yang | 2015-12-01 |
| 9171926 | Channel doping extension beyond cell boundaries | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2015-10-27 |
| 9141745 | Method and system for designing Fin-FET semiconductor device | Chung-Min Fu, Yung-Fong Lu | 2015-09-22 |
| 9129956 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Ching-Wei Wu, Jui-Che Tsai +1 more | 2015-09-08 |
| 9122839 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam | 2015-09-01 |
| 9111065 | Method for dummy metal and dummy via insertion | Hung-Yi Liu, Chih-Chieh Chen, Jian-Yi Li | 2015-08-18 |
| 9058462 | System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE) | King-Ho Tam, Yeh-Chi Chang, Kuo-Nan Yang, Zhe-Wei Jiang | 2015-06-16 |
| 9047433 | Cell and macro placement on fin grid | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2015-06-02 |
| 9026953 | Compression method and system for use with multi-patterning | Huang-Yu Chen, Chin-Hsiung Hsu, Wen-Hao Chen | 2015-05-05 |
| 8990762 | Semiconductor device design method, system and computer program product | Ping-Hung Yuh, Cheng-I Huang | 2015-03-24 |
| 8977991 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Wen-Hao Chen, Yi-Kan Cheng | 2015-03-10 |
| 8937358 | Channel doping extension beyond cell boundaries | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2015-01-20 |
| 8914755 | Layout re-decomposition for multiple patterning layouts | Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Yen-Pin Chen, Wen-Hao Chen | 2014-12-16 |
| 8847284 | Integrated circuit with standard cells | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2014-09-30 |
| 8850368 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Yi-Kan Cheng | 2014-09-30 |
| 8826195 | Layout modification method and system | Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam | 2014-09-02 |
| 8826212 | Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed | Sung-Yen Yeh, Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam +1 more | 2014-09-02 |
| 8816486 | Pad structure for 3D integrated circuit | Chih Sheng Tsai | 2014-08-26 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang +2 more | 2014-08-19 |
| 8769451 | Semiconductor device design method, system and computer program product | Ping-Hung Yuh, Cheng-I Huang | 2014-07-01 |
| 8732641 | Pattern matching based parasitic extraction with pattern reuse | Ping-Hung Yuh, Hsin-Yun Lin, Cheng-I Huang | 2014-05-20 |
| 8726212 | Streamlined parasitic modeling with common device profile | Cheng-I Huang, Hsiao-Shu Chao | 2014-05-13 |
| 8694945 | Automatic place and route method for electromigration tolerant power distribution | King-Ho Tam, Huang-Yu Chen | 2014-04-08 |
| 8671367 | Integrated circuit design in optical shrink technology node | Lee-Chung Lu, Yung-Chin Hou, Lie-Szu Juang | 2014-03-11 |