Issued Patents All Time
Showing 101–125 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10565341 | Constrained cell placement | Yen-Hung Lin, Yuan-Te Hou | 2020-02-18 |
| 10515166 | Method of timing analysis | Yen-Pin Chen, Tai-Yu Cheng, Tzu-Hen Lin | 2019-12-24 |
| 10515944 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2019-12-24 |
| 10515178 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Kuo-Nan Yang, Yi-Kan Cheng | 2019-12-24 |
| 10515175 | Block-level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2019-12-24 |
| 10509888 | System and method for forming integrated device | Hiranmay Biswas, Kuo-Nan Yang | 2019-12-17 |
| 10509886 | Method, system, and storage medium for RC extraction using hierarchical modeling architecture | Chin-Shen Lin, Meng-Xiang Lee, Kuo-Nan Yang | 2019-12-17 |
| 10503849 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Sung-Yen Yeh, Li-Chung Hsu | 2019-12-10 |
| 10489547 | Multiple patterning method, system for implementing the method and layout formed | Yen-Hung Lin, Yuan-Te Hou | 2019-11-26 |
| D866638 | Camera | Bo Huang, Tsung-Ti Liu | 2019-11-12 |
| 10467364 | Characterizing cell using input waveforms with different tail characteristics | King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen | 2019-11-05 |
| D861763 | Camera | Tsung-Ti Liu | 2019-10-01 |
| 10360337 | Method of forming conductive grid of integrated circuit | Hiranmay Biswas, Kuo-Nan Yang | 2019-07-23 |
| 10268791 | System and method for multi-patterning | Yen-Hung Lin, Chin-Chou Liu, Chi Wei Hu | 2019-04-23 |
| 10176284 | Semiconductor circuit design and manufacture method | Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Yen-Pin Chen | 2019-01-08 |
| 10169506 | Circuit design method and system | King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2019-01-01 |
| 10157258 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2018-12-18 |
| 10157257 | Method for analyzing an electromigration (EM) rule violation in an integrated circuit | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang | 2018-12-18 |
| 10157254 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Yi-Kan Cheng, Kumar Lalgudi | 2018-12-18 |
| 10157840 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10074641 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2018-09-11 |
| 10055531 | Layout checking method for advanced double patterning photolithography with multiple spacing criteria | King-Ho Tam, Yuan-Te Hou, Chin-Chang Hsu, Meng-Kai Hsu | 2018-08-21 |
| 10050028 | Semiconductor device with reduced leakage current | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Yi-Hsun Chiu +1 more | 2018-08-14 |
| 9984192 | Cell having shifted boundary and boundary-shift scheme | Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao | 2018-05-29 |
| 9953122 | Integrated circuit design method and associated non-transitory computer-readable medium | Yu-Jen Chang, Kuo-Nan Yang, Jui-Jung Hsu, Chih-Hung Wu | 2018-04-24 |