Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223247 | Logic cell structures and related methods | Ranjith Kumar, Mohammed Rabiul Islam, Jianyang Xu | 2025-02-11 |
| 11816412 | Logic cell structures and related methods | Ranjith Kumar, Mohammed Rabiul Islam, Jianyang Xu | 2023-11-14 |
| 11239163 | Tapering discrete interconnection for an integrated circuit (IC) | Jaskirat Bindra | 2022-02-01 |
| 11201610 | Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs | Jaskirat Bindra | 2021-12-14 |
| 10819325 | Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs | Jaskirat Bindra | 2020-10-27 |
| 10748849 | Tapering discrete interconnection for an integrated circuit (IC) | Jaskirat Bindra | 2020-08-18 |
| 10678990 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng | 2020-06-09 |
| 10476490 | Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs | Jaskirat Bindra | 2019-11-12 |
| 10276497 | Tapering discrete interconnection for an integrated circuit (IC) | Jaskirat Bindra | 2019-04-30 |
| 10157254 | Techniques based on electromigration characteristics of cell interconnect | Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng | 2018-12-18 |
| 9799602 | Integrated circuit having a staggered fishbone power network | Kuang-Hung Chang, Wen-Hao Chen, Yuan-Te Hou | 2017-10-24 |
| 7350174 | Method and apparatus for layout synthesis of regular structures using relative placement | Vinoo N. Srinivasan, Veerapaneni Nagbhushan | 2008-03-25 |
| 7266792 | Automated noise convergence for cell-based integrated circuit design | Prashant Saxena | 2007-09-04 |
| 6757878 | Method and apparatus for layout synthesis of regular structures using relative placement | Vinoo N. Srinivasan, Veerapaneni Nagbhushan | 2004-06-29 |