VN

Veerapaneni Nagbhushan

IN Intel: 3 patents #10,349 of 30,777Top 35%
📍 Saratoga, CA: #1,541 of 2,933 inventorsTop 55%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,580,772 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
7376922 Method and apparatus for integrated circuit datapath layout using a vector editor John A. Rushing 2008-05-20
7350174 Method and apparatus for layout synthesis of regular structures using relative placement Vinoo N. Srinivasan, Kumar Lalgudi 2008-03-25
6757878 Method and apparatus for layout synthesis of regular structures using relative placement Vinoo N. Srinivasan, Kumar Lalgudi 2004-06-29