Issued Patents All Time
Showing 176–200 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8661395 | Method for dummy metal and dummy via insertion | Hung-Yi Liu, Chih-Chieh Chen, Jian-Yi Li | 2014-02-25 |
| 8601409 | Compression method and system for use with multi-patterning | Huang-Yu Chen, Chin-Hsiung Hsu, Wen-Hao Chen | 2013-12-03 |
| 8601408 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Wen-Hao Chen, Yi-Kan Cheng | 2013-12-03 |
| 8547131 | System and method for observing threshold voltage variations | Chih-Chieh Chen, Yi-Wei Chen | 2013-10-01 |
| 8539396 | Stitch and trim methods for double patterning compliant standard cell design | Chin-Hsiung Hsu, Huang-Yu Chen | 2013-09-17 |
| 8504965 | Method for non-shrinkable IP integration | Hung-Yi Liu, Yung-Chin Hou, Lie-Szu Juang | 2013-08-06 |
| 8499274 | Computer implemented system and method for leakage calculation | Chien-Ju Chao, Jerry Chang Jui Kao, King-Ho Tam, Huan Chi Tseng | 2013-07-30 |
| 8453095 | Systems and methods for creating frequency-dependent netlist | Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng +1 more | 2013-05-28 |
| 8448100 | Tool and method for eliminating multi-patterning conflicts | Hung-Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao +5 more | 2013-05-21 |
| 8418117 | Chip-level ECO shrink | Huang-Yu Chen, Ho Che Yu, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu | 2013-04-09 |
| 8359554 | Verification of 3D integrated circuits | Chih Sheng Tsai, Ying-Lin Liu, Kai-Yun Lin | 2013-01-22 |
| 8347132 | System and method for reducing processor power consumption | Lee-Chung Lu, Myron Shak, Wei-Pin Changchien, Kuo-Yin Chen, Chi Wei Hu +2 more | 2013-01-01 |
| 8307321 | Method for dummy metal and dummy via insertion | Hung-Yi Liu, Chih-Chieh Chen, Jian-Yi Li | 2012-11-06 |
| 8252489 | Mask-shift-aware RC extraction for double patterning design | Ke-Ying Su, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng | 2012-08-28 |
| 8239802 | Robust method for integration of bump cells in semiconductor device design | Hung-Yi Liu, Agrawal Aditya Binodkumar | 2012-08-07 |
| 8232824 | Clock circuit and method for pulsed latch circuits | Chih-Chieh Chen, Chih Sheng Tsai, Shu-Yi Ying | 2012-07-31 |
| 8117575 | System and method for on-chip-variation analysis | Lee-Chung Lu, Yuan-Te Hou | 2012-02-14 |
| 8060843 | Verification of 3D integrated circuits | Chih Sheng Tsai, Ying-Lin Liu, Kai-Yun Lin | 2011-11-15 |
| 7966596 | Place-and-route layout method with same footprint cells | Lee-Chung Lu, Ping Li, Chun-Hui Tai, Li-Chun Tien, Gwan Sin Chang | 2011-06-21 |
| 7913141 | Power gating in integrated circuits for leakage reduction | Lee-Chung Yu, Yung-Chin Hou | 2011-03-22 |
| 7793130 | Mother/daughter switch design with self power-up control | Shih-Hsien Yang, Lee-Chung Lu, Chun-Hui Tai, Cliff Hou | 2010-09-07 |
| 7640520 | Design flow for shrinking circuits having non-shrinkable IP layout | Lee-Chung Lu, Cliff Hou, Lie-Szu Juang | 2009-12-29 |
| 7596737 | System and method for testing state retention circuits | Lee-Chung Lu | 2009-09-29 |
| 6862723 | Methodology of generating antenna effect models for library/IP in VLSI physical design | Daisy Wang, Chia-Ling Cheng, Lee-Chung Lu, Cliff Hou | 2005-03-01 |
| 6789248 | Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization | Lee-Chung Lu, Cliff Hou, Chia-Lin Cheng, Hsing-Chien Huang, Yee-Wen Chen +1 more | 2004-09-07 |