Issued Patents All Time
Showing 26–50 of 201 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11935833 | Method of forming power grid structures | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin | 2024-03-19 |
| 11929331 | Routing structure | Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang | 2024-03-12 |
| 11907007 | Clock signal distribution system, integrated circuit device and method | Jerry Chang Jui Kao, Huang-Yu Chen, Sheng-Hsiung Chen, Jack Liu, Yung-Chen Chien +1 more | 2024-02-20 |
| 11908853 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2024-02-20 |
| 11893333 | Hybrid sheet layout, method, system, and structure | Shang-Wei Fang, Kam-Tou Sio, Wei-Cheng Lin, Jiann-Tyng Tzeng, Lee-Chung Lu +1 more | 2024-02-06 |
| 11861284 | Conductor scheme selection and track planning for mixed-diagonal-manhattan routing | Sheng-Hsiung Chen, Huang-Yu Chen, Jerry Chang Jui Kao | 2024-01-02 |
| 11853678 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2023-12-26 |
| 11816413 | Systems and methods for context aware circuit design | Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang Jui Kao | 2023-11-14 |
| 11809803 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2023-11-07 |
| 11783106 | Circuit testing and manufacture using multiple timing libraries | Ravi Babu Pittu, Sung-Yen Yeh, Li-Chung Hsu | 2023-10-10 |
| 11775725 | System and computer program product for integrated circuit design | Chin-Shen Lin, Hiranmay Biswas, Kuo-Nan Yang | 2023-10-03 |
| 11769766 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Yi-Kan Cheng | 2023-09-26 |
| 11748542 | Systems and methods for integrated circuit layout | Sheng-Hsiung Chen, Chun-Chen Chen, Shao-Huan Wang, Kuo-Nan Yang, Ren-Zheng Liao +1 more | 2023-09-05 |
| 11727183 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2023-08-15 |
| 11720738 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou | 2023-08-08 |
| 11715733 | Integrated circuit device and method | Wei-Ren Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Yung-Chen Chien, Jerry Chang Jui Kao +1 more | 2023-08-01 |
| 11714949 | Leakage analysis on semiconductor device | Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou | 2023-08-01 |
| 11704469 | Integrated circuit and method of forming the same | John Lin, Chin-Shen Lin, Kuo-Nan Yang | 2023-07-18 |
| 11669671 | Semiconductor device including PG-aligned cells and method of generating layout of same | Hiranmay Biswas, Kuo-Nan Yang | 2023-06-06 |
| 11669669 | Circuit layouts and related methods | Chin-Shen Lin, Wan-Yu Lo, Shao-Huan Wang, Kuo-Nan Yang, Sheng-Hsiung Chen +1 more | 2023-06-06 |
| 11651136 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2023-05-16 |
| 11600568 | Layouts for conductive layers in integrated circuits | Wan-Yu Lo, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan +1 more | 2023-03-07 |
| 11593546 | Integrated circuit with thicker metal lines on lower metallization layer | Kuang-Hung Chang, Yuan-Te Hou, Yung-Chin Hou | 2023-02-28 |
| 11574108 | Block level design method for heterogeneous PG-structure cells | Yen-Hung Lin, Yuan-Te Hou | 2023-02-07 |
| 11574106 | Method, system, and storage medium of resource planning for designing semiconductor device | Yen-Hung Lin, Yuan-Te Hou | 2023-02-07 |