Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9292645 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2016-03-22 |
| 9223924 | Method and system for multi-patterning layout decomposition | Chin-Hsiung Hsu, Chin-Chang Hsu, Godina Ho, Wen-Hao Chen, Wen-Ju Yang | 2015-12-29 |
| 9117882 | Non-hierarchical metal layers for integrated circuits | Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien, Dian-Hau Chen | 2015-08-25 |
| 9087170 | Cell layout design and method | Chin-Hsiung Hsu, Li-Chun Tien, Hui-Zhong Zhuang, Fang-Yu Fan, Wen-Hao Chen +1 more | 2015-07-21 |
| 9064081 | Generating database for cells routable in pin layer | Meng-Kai Hsu, Chi-Yeh Yu, Wen-Hao Chen | 2015-06-23 |
| 9035361 | Electromigration resistant standard cell device | Lee-Chung Lu, Wen-Hao Chen, Shen-Feng Chen, Meng-Fu You | 2015-05-19 |
| 8977991 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2015-03-10 |
| 8972910 | Routing method | Wen-Hao Chen, Chin-Hsiung Hsu, Meng-Kai Hsu | 2015-03-03 |
| 8959466 | Systems and methods for designing layouts for semiconductor device fabrication | Chin-Hsiung Hsu, Wen-Hao Chen | 2015-02-17 |
| 8914755 | Layout re-decomposition for multiple patterning layouts | Chin-Hsiung Hsu, Huang-Yu Chen, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang | 2014-12-16 |
| 8907441 | Methods for double-patterning-compliant standard cell design | Huang-Yu Chen, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng +2 more | 2014-12-09 |
| 8907497 | Semiconductor device with self-aligned interconnects and blocking portions | Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan | 2014-12-09 |
| 8898600 | Layout optimization for integrated design | Huang-Yu Chen, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2014-11-25 |
| 8875067 | Reusable cut mask for multiple layers | Chin-Hsiung Hsu, Huang-Yu Chen, Wen-Hao Chen | 2014-10-28 |
| 8856696 | Integrated circuit layout modification | Wen-Hao Chen, Yi-Kan Cheng | 2014-10-07 |
| 8850368 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng | 2014-09-30 |
| 8826212 | Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed | Sung-Yen Yeh, Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam +1 more | 2014-09-02 |
| 8631366 | Integrated circuit design using DFM-enhanced architecture | Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai +1 more | 2014-01-14 |
| 8601408 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng | 2013-12-03 |
| 8584052 | Cell layout for multiple patterning technology | Huang-Yu Chen, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu | 2013-11-12 |
| 8448100 | Tool and method for eliminating multi-patterning conflicts | Hung-Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao +5 more | 2013-05-21 |
| 8431968 | Electromigration resistant standard cell device | Lee-Chung Lu, Wen-Hao Chen, Shen-Feng Chen, Meng-Fu You | 2013-04-30 |
| 8418111 | Method and apparatus for achieving multiple patterning technology compliant design layout | Huang-Yu Chen, Fang-Yu Fan, Lee-Chung Lu, Ru-Gun Liu, Ken-Hsien Hsieh +3 more | 2013-04-09 |
| 8255837 | Methods for cell boundary isolation in double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Yung-Chin Hou, Li-Chun Tien | 2012-08-28 |
| 8239806 | Routing system and method for double patterning technology | Huang-Yu Chen, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng +1 more | 2012-08-07 |