Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11914941 | Integrated circuit layout validation using machine learning | Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang | 2024-02-27 |
| 11010529 | Integrated circuit layout validation using machine learning | Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang | 2021-05-18 |
| 10909297 | Deterministic system for device layout optimization | Chin-Chang Hsu, Chien-Te Wu | 2021-02-02 |
| 8219944 | Method and system performing block-level RC extraction | Li Song, Zhan-Zhong Yao, Hao Ji, Taber H. Smith | 2012-07-10 |