Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361199 | Integrated circuit layout generation method | Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more | 2025-07-15 |
| 12135930 | Integrated circuit layout generation method and system | Ke-Ying Su, Ke-Wei Su, Keng-Hua KUO | 2024-11-05 |
| 11907636 | Integrated circuit layout generation method | Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more | 2024-02-20 |
| 11842135 | Integrated circuit layout generation method and system | Ke-Ying Su, Ke-Wei Su, Keng-Hua KUO | 2023-12-12 |
| 11392749 | Integrated circuit layout generation method and system | Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more | 2022-07-19 |
| 10860769 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su +2 more | 2020-12-08 |
| 10846456 | Integrated circuit modeling methods and systems | Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more | 2020-11-24 |
| 10796059 | Integrated circuit layout generation method and system | Ke-Ying Su, Ke-Wei Su, Keng-Hua KUO | 2020-10-06 |
| 10521538 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Chen, Ke-Wei Su +2 more | 2019-12-31 |