Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8904314 | RC extraction for multiple patterning layout design | Chia-Ming Ho, Te-Yu Liu, Hsien-Hsin Sean Lee | 2014-12-02 |
| 8887106 | Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process | Chia-Ming Ho, Hsiao-Shu Chao, Yi-Kan Cheng | 2014-11-11 |
| 8887116 | Flexible pattern-oriented 3D profile for advanced process nodes | Chia-Ming Ho, Te-Yu Liu, Austin Chingyu Chiang, Meng-Fan Wu | 2014-11-11 |
| 8826213 | Parasitic capacitance extraction for FinFETs | Chia-Ming Ho, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee | 2014-09-02 |
| 8793640 | Methods and apparatus for RC extraction | Te-Yu Liu, Austin Chingyu Chiang, Hsiao-Shu Chao | 2014-07-29 |
| 8751975 | RC corner solutions for double patterning technology | Hsiao-Shu Chao, Yi-Kan Cheng | 2014-06-10 |
| 8745559 | Systems and methods for creating frequency-dependent netlist | Chih-Cheng Chou | 2014-06-03 |
| 8732628 | Method and system for photomask assignment for double patterning technology | Meng-Fan Wu, I-Fan Lin, Hsiao-Shu Chao, Yi-Kan Cheng | 2014-05-20 |
| 8671382 | Method of generating RC technology file | Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou | 2014-03-11 |
| 8607179 | RC extraction methodology for floating silicon substrate with TSV | Ze-Ming Wu, Ching-Shun Yang, Hsiao-Shu Chao | 2013-12-10 |
| 8572537 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen | 2013-10-29 |
| 8495532 | Systems and methods for creating frequency-dependent RC extraction netlist | Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng | 2013-07-23 |
| 8453095 | Systems and methods for creating frequency-dependent netlist | Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen +1 more | 2013-05-28 |
| 8418112 | Method of generating RC technology file | Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou | 2013-04-09 |
| 8336002 | IC design flow enhancement with CMP simulation | Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu | 2012-12-18 |
| 8252489 | Mask-shift-aware RC extraction for double patterning design | Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng | 2012-08-28 |
| 8214784 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen | 2012-07-03 |
| 8119310 | Mask-shift-aware RC extraction for double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Cheng-Hung Yeh, Dian-Hau Chen +2 more | 2012-02-21 |
| 7818698 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Chia-Ming Ho, Gwan Sin Chang, Chien-Wen Chen | 2010-10-19 |