Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9507897 | Circuit arrangement for modeling transistor layout characteristics | Yi Wang, Chia-Ying Lin, Run Gao, Hung-Han Lin, Chia-Chi Ho | 2016-11-29 |
| 9239898 | Circuit simulation with rule check for device | Hsien-Ming Chen, Yi Wang, Jian-Zhi Huang, Chia-Ying Lin, Chia-Chi Ho +2 more | 2016-01-19 |
| 7028277 | Process related deviation corrected parasitic capacitance modeling method | Victor Chih Yuan Chang, Chien-Wen Chen, Harry Chuang, Hsin-Yi Lee, Yu-Tai Chia | 2006-04-11 |
| 6800496 | Characterization methodology for the thin gate oxide device | Ke-Wei Su, Chung-Kai Lin, Jaw-Kang Her, Yu-Tai Chia | 2004-10-05 |