Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381158 | Wafer bonding method and bonded device structure | Yuan-Jen Lee, Nuo Xu, Fang-Lan Chu, Wei-Cheng Wu | 2025-08-05 |
| 12278166 | High bandwidth package structure | Wen-Tuo Huang, Wei-Cheng Wu, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung | 2025-04-15 |
| 8487382 | Device scheme of HKMG gate-last process | Sheng-Chen Chung, Kong-Beng Thei | 2013-07-16 |
| 8174091 | Fuse structure | Kong-Beng Thei, Chung Long Cheng, Chung-Shi Liu, Shien-Yang Wu, Shi-Bai Chen | 2012-05-08 |
| 8138554 | Semiconductor device with local interconnects | Kong-Beng Thei, Sheng-Chen Chung, Mong-Song Liang | 2012-03-20 |
| 8115271 | Reducing device performance drift caused by large spacings between active regions | Kong-Beng Thei, Mong-Song Liang | 2012-02-14 |
| 7833848 | Method for removing hard masks on gates in semiconductor manufacturing process | Hung-Chih Tsai, Chih-Chieh Chen, Sheng-Chen Chung, Kong-Beng Thei | 2010-11-16 |
| 7812379 | SOI devices | Chung Long Cheng, Kong-Beng Thei, Sheng-Chen Chung, Tzung-Chi Lee | 2010-10-12 |
| 7803674 | Methods for fabricating SOI devices | Chung Long Cheng, Kong-Beng Thei, Sheng-Chen Chung, Tzung-Chi Lee | 2010-09-28 |
| 7632729 | Method for semiconductor device performance enhancement | Kong-Beng Thei, Chung Long Cheng, Sheng-Chen Chung, Wen-Huei Guo, Jung-Hui Kao +2 more | 2009-12-15 |
| 7550795 | SOI devices and methods for fabricating the same | Chung Long Cheng, Kong-Beng Thei, Sheng-Chen Chung, Tzung-Chi Lee | 2009-06-23 |
| 7407835 | Localized slots for stress relieve in copper | — | 2008-08-05 |
| 7332756 | Damascene gate structure with a resistive device | Chung Long Cheng, Kong-Beng Thei | 2008-02-19 |
| 7298011 | Semiconductor device with recessed L-shaped spacer and method of fabricating the same | Kong-Beng Thei, Chung Long Cheng | 2007-11-20 |
| 7154182 | Localized slots for stress relieve in copper | — | 2006-12-26 |
| 7030497 | Localized slots for stress relieve in copper | — | 2006-04-18 |
| 7028277 | Process related deviation corrected parasitic capacitance modeling method | Victor Chih Yuan Chang, Chung-Shi Chiang, Chien-Wen Chen, Hsin-Yi Lee, Yu-Tai Chia | 2006-04-11 |
| 6867441 | Metal fuse structure for saving layout area | Chao-Hsiang Yang, Charles Chen, Wesley Lin, Ming Li, Jeng-Long Huang | 2005-03-15 |
| 6854100 | Methodology to characterize metal sheet resistance of copper damascene process | Victor Chih Yuan Chang, Yung-Shun Chen, Shang-Yun Hou | 2005-02-08 |
| 6831349 | Method of forming a novel top-metal fuse structure | — | 2004-12-14 |
| 6828223 | Localized slots for stress relieve in copper | — | 2004-12-07 |
| 6638796 | Method of forming a novel top-metal fuse structure | — | 2003-10-28 |